WO2005093575A1 - Appareil de verification dynamique permettant d'obtenir une performance et une efficacite de verification elevees et procede de verification associe - Google Patents

Appareil de verification dynamique permettant d'obtenir une performance et une efficacite de verification elevees et procede de verification associe Download PDF

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WO2005093575A1
WO2005093575A1 PCT/KR2005/000668 KR2005000668W WO2005093575A1 WO 2005093575 A1 WO2005093575 A1 WO 2005093575A1 KR 2005000668 W KR2005000668 W KR 2005000668W WO 2005093575 A1 WO2005093575 A1 WO 2005093575A1
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Prior art keywords
simulation
verification
design
runs
abstraction
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PCT/KR2005/000668
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English (en)
Inventor
Seiyang Yang
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Seiyang Yang
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Priority claimed from KR1020040017476A external-priority patent/KR20040063845A/ko
Priority claimed from KR1020040093309A external-priority patent/KR20050090053A/ko
Priority claimed from KR1020050007330A external-priority patent/KR20050118107A/ko
Application filed by Seiyang Yang filed Critical Seiyang Yang
Priority to US10/591,910 priority Critical patent/US20080306721A1/en
Priority to JP2007502715A priority patent/JP2007528553A/ja
Publication of WO2005093575A1 publication Critical patent/WO2005093575A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Definitions

  • the present invention relates to a technique for verifying a digital circuit or a digital system, and more particularly, to a verification apparatus which is capable of verifying a digital circuit or a digital system using a verification apparatus for system integration circuit design, and a method using the same. Even more particularly, the present invention relates to the verification apparatus which can increase the verification performance and reduce the verification time, and a method using the same.
  • the present invention relates to a technique for verifying a digital system having at least several million gates, and more specifically to a verification apparatus which increases the verification performance and efficiency when a digital system having at least several million gates is verified by simulation, and a method using the same.
  • DUV Design Under Verification
  • TB test bench
  • HDL Hardware Description Language
  • SDL System Description Language
  • HVL Hardware Verification Language
  • HDL simulators for example, Verilog simulator, VHDL simulator, Syste Verilog simulator, etc
  • SDL simulators for example, SystemC simulator, HW/SW co-simulator, etc
  • Vera simulator for example, Vera simulator, e simulator, etc
  • Vera simulator for example, Vera simulator, e simulator, etc
  • the simulator must execute the software code consisting of instruction sequence, which models the circuit to be verified and the test bench, sequentially on a computer
  • the degradation of simulation performance is inversely proportional to the size of design. For example, many 10 million- gate designs are running in either a HDL simulator or a SDL simulator on the computer having the fastest processor at the speed of 10-100 cycles/sec range at RTL, and 1 -10 cycles/sec range at gate level at most.
  • the total simulation cycles is needed in the range of a couple of million to a couple of billion to verify the design, the total simulation takes prohibitively long. There are some technologies that can reduce this long verification time.
  • the first is to use a hardware-assisted verification system (such as simulation accelerator, hardware emulator, FPGA prototyping system, etc), and the second is to use a simulation farm which consist of multiple HDL simulators on one or more computers (for example, 100 units of workstations) in a high speed network.
  • a hardware-assisted verification system such as simulation accelerator, hardware emulator, FPGA prototyping system, etc
  • a simulation farm which consist of multiple HDL simulators on one or more computers (for example, 100 units of workstations) in a high speed network.
  • hardware-assisted verification systems cannot be used in the early design phase, their synthesis or compilation process takes much longer than that of HDL simulators, their use is much harder than HDL simulators, their purchasing and maintenance/repairing costs are large, and most of all, HDL simulators are much more favorable than hardware-assisted verification systems to either designers or verification engineers.
  • test bench Even worse, as the complexity of test bench is kept on increasing because there are varieties of components existing inside TB (for example, random stimulus generators, monitors, checkers, coverage tools, response checkers, etc), which is described in higher level of abstraction, the increased TB overhead is one of main components that constitute the slow down of simulation performance.
  • the various test benches, or in some cases, some components in DUV are absolutely necessary in test bench automation, coverage-driven verification, or assertion-driven verification for recent advanced verification technology, but their use results in the slow down of simulation significantly. Even worse, throughout using the advanced verification technology, only the existence of bugs in the design can be determined, or at best the possible buggy areas in the design can be known, but not possible to identify the exact location of bugs in the design.
  • Intelligent human can be only responsible for identifying and eliminating the bugs in the design. To do this, the designers or verification engineers need to examine the signals or variables in DUV, and even in TB occasionally after probing them during the simulation. However, when these two situations exist together, the speed of simulation is degraded even more. Also, when TB is described in HVL, API(Application Program Interface) of HDL simulators, VPI/PLI/FLI, must be used in general, their use makes the simulation speed even slower. More over, the most of designs starts at the register transfer level (abbreviated RTL afterward), and are synthesized into a net-list by some logic synthesis technology.
  • RTL afterward register transfer level
  • DUV described at RTL is too slow to be a platform for developing embedded software, but software developers need a platform on which their software can be executed fast enough for the development during the hardware design is under way.
  • event-driven simulation there are cycle-based simulation, and transaction simulation.
  • event-driven technique is less abstract than cycle-based one
  • cycle-based one is less abstract than transaction-based one.
  • Cycle-based simulation is about 10-100 times faster than event-driven simulation, but imposes many constraints on the designs. Therefore, hardware designers are completely ignoring any cycle-based simulations and favorably using some event-driven simulations.
  • event-driven simulation, cycle-based simulation, and transaction-based simulation are used separately. Overall, these situations greatly hinder the verification with the high efficiency and performance.
  • the purpose of the present invention is to provide a simulation-based design verification apparatus and a design verification method by using it for designing very large scaled digital systems. More specifically, the technology in the present invention is about the verification apparatus which uses simulation, and if necessary, formal verification, simulation acceleration, hardware emulation, and(or) prototyping (called a verification platform in a common name) together to increase the efficiency and performance of verification for verifying at least multi-million gate digital designs, and the verification method using the same.
  • a verification platform in a common name formal verification, simulation acceleration, hardware emulation, and(or) prototyping
  • One of the objectives in the present invention is to provide an automatic method and a verification apparatus for it which can identify the locations of bugs in the design code while reducing the simulation time, compared to the traditional methods which require dumping all signals and variables in the design code at the beginning of simulation.
  • Another objective in the present invention is to provide an automatic method and a verification apparatus for it which maintains the high visibility with the high performance when using test bench automation, coverage-driven verification, or assertion-based verification together with simulation • in advanced verification.
  • another objective in the present invention is to provide an automatic method and a verification apparatus for it which keeps the high visibility for DUV, and simultaneously reduces the total simulation time greatly by using the simulation results of the higher abstraction level in the simulation at the lower abstraction level in the top-down design process. This eventually contributes to the efficient hardware verification, software verification, or hardware/software co-verification. Still, another objective in the present invention is to increase the overall verification performance and efficiency existed in the different level of abstractions by using the verification results of a higher level of design abstraction in the verification at a lower level of design abstraction through an automatic way, thereby accelerating the verification at the lower level of design abstraction, and if necessary increasing the verification efficiency at the lower level of design abstraction utilizing the verification results of the higher level of abstraction as a reference.
  • another objective in the present invention is to increase the overall verification performance and efficiency existed in the different level of abstractions by using the verification results of a higher level of design abstraction in the verification at a lower level of design abstraction through an automatic way, thereby accelerating the verification at the lower level of design abstraction, and if necessary increasing the verification efficiency at the higher level of design abstraction utilizing the verification results of the lower level of abstraction as a reference. Still, another objective in the present invention is to increase the overall verification performance and efficiency by selectively using transaction-level simulation, cycle-based simulation, or(and) event-driven simulation in the optimal way in the process of the verification flow from top level of design abstraction to bottom-level of design abstraction, and using the verification results of a specific level of design abstraction in the verification at a different level of design abstraction. Still, another objective in the present invention is to increase the total verification performance and efficiency by using at least one or more of formal verification, simulation acceleration, hardware emulation, or prototyping together with simulation.
  • FIG. 1 is an example of the schematic view of the design verification apparatus in accordance with the present invention
  • FIG. 2 is another example of the schematic view of the design verification apparatus in accordance with the present invention
  • FIG 3 is a schematic view of a simulation process by the method proposed in the present invention
  • FIG. 4 is a schematic view of a bug finding and removing process throughout the simulation proposed in the present invention, which consists of the 1 st simulation as the front-stage simulation and the post-1 sl simulations as the back-stage simulation
  • FIG. 5(a) is a schematic view showing a verification process in the verification using the apparatus showing in FIG. 1 or FIG. 2
  • FIG. 5(b) is a schematic view showing another verification process in the verification using the apparatus showing in FIG. 1 or FIG.
  • FIG. 6(a) is a schematic view showing a verification process in which the post-1 * simulations as the back-stage simulation are executed in parallel, using the verification apparatus in FIG. 2
  • FIG. 6(b) is a schematic view showing another verification process, in which the post-1 st simulations as the back-stage simulation are executed in parallel, using the -,
  • verification apparatus in FIG. 2 is a schematic view showing another verification process, in which the post-1 " simulations as the back-stage simulation are executed in parallel, using the verification apparatus in FIG. 2
  • FIG. 6(d) is a schematic view showing another verification process, in which the post-1 st simulations as the back-stage simulation are executed in parallel, using the verification apparatus in FIG. 2;
  • FIG. 6(d) is a schematic view showing another verification process, in which the post-1 st simulations as the back-stage simulation are executed in parallel, using the verification apparatus in FIG. 2;
  • FIG. 2 is a schematic view showing a verification process in which the post-1 * simulations as the back
  • FIG. 7 is another example of the schematic view of the design verification apparatus in accordance with the present invention
  • FIG. 8 is an example of the schematic view of the design verification apparatus in accordance with the present invention which consists of verification software of the present invention, at least one computer having at least one simulator, and at least one hardware-assisted verification platform
  • FIG. 9 is an example of the schematic view of the design verification apparatus in accordance with the present invention which consists of verification software of the present invention, at least two computers having at least two simulators, at least one hardware-assisted verification platform, and a computer network which connects among them;
  • FIG. 10 is an another example of the schematic view of the design verification apparatus in accordance with the present invention which consists of verification software of the present invention, at least one computer having at least one simulator, and at least one hardware-assisted verification platform;
  • FIG. 11 is an example of the schematic view showing the reuse of the previous verification results in the verification using the apparatus in FIG. 8;
  • FIG. 12 is an example of the schematic view showing the reuse of the previous simulation results in the verification using the apparatus in FIG. 1 ;
  • FIG. 13 is an example of the schematic view showing the fast execution of verification process by re-using the verification results of any design objects unaltered on an arbitrary verification platform after some design objects are modified;
  • FIG. 11 is an example of the schematic view showing the reuse of the previous verification results in the verification using the apparatus in FIG. 8
  • FIG. 12 is an example of the schematic view showing the reuse of the previous simulation results in the verification using the apparatus in FIG. 1
  • FIG. 13 is an example of the schematic view showing the fast execution of verification process by re-using the verification results of
  • FIG. 14 is an example of the schematic view showing the fast execution of verification process by re-using the verification results of any design objects unaltered on an arbitrary hardware-assisted verification platform after some design objects are modified
  • FIG. 15 is an example of the schematic view showing the fast execution of simulation process by re-using the simulation results of any design objects unaltered on a simulator after some design objects are modified
  • Test bench design object 14 DUV design object 16: Design block design object 15: Input information for replay 20: Design object modified 22: Partial dynamic information collected before the design change 27: Hardware-assisted verification platform 28: A system software component in a prototyping system 29: A system software component in a simulation accelerator 30: A system software component in a hardware emulator 31: The software module in the verification software which instruments either the additional code or the additional circuit to either a design code or a synthesized net-list in an automatic way 32: Verification software 34: Simulator 35: Computer 36: A hardware component in a hardware emulator platform 37: A hardware component in a simulation accelerator platform 38: A hardware component in a prototyping system platform 42: Model checker or property checker 44: The software module in the verification software which is in charge of transferring files or data among more than one computers during the verification, executing the 1 st verification run, preparing the post-1 sl verification runs, and executing the post-1 3 ' verification runs.
  • the design verification apparatus of the present invention provides a verification software, one or more computer installed one or more verification platform (simulators, for example).
  • the verification software is executed in a computer, and if there are more than one computer in a said design verification apparatus, those computers can transfer the files among them as they are connected in a computer network.
  • Said one or more verification platform could be simulators, simulation accelerators, formal verification tools such as model checkers or property checkers, hardware emulators, or prototyping systems, but from now on they are meant simulator otherwise specifically mentioned.
  • said one or more verification platform is(are) simulator(s)
  • they could be event-driven simulators, event-driven simulators and cycle-based simulators, cycle-based simulators, cycle-based simulators and transaction-based simulators, or event-driven simulators and cycle-based simulators and transaction-based simulators.
  • the verification apparatus and verification method proposed in the present invention can be used both the gate-level verification using synthesized net-lists, the and timing verification using timing information back-annotated from the placement and routing to the gate-level net- list as well as the functional verification using original design codes.
  • the detailed description is mainly focused on the functional verification because same techniques are easily applicable to gate-level verification or timing verification as well.
  • the functional verification can be done at RTL(Register Transfer Level), but also durable at behavioral-level or transaction-level which is even higher abstraction level than RTL. But, the detailed description is also assumed that the functional verification is at RTL mostly.
  • the proposed method can be even applicable to the hybrid-level of verification which spans more than one design abstraction level.
  • Said verification software instruments the additional code or circuit after reading the design codes in an automatic way.
  • the instrumented code or circuit are basically additional HDL codes, SDL codes, HVL codes, C/C++ codes, simulation commands, or even more than one of those.
  • simulation states or the states of design objects (to be explained later) which needs the visibility in DU and even the states of TB in some cases at the regular interval or more than one discrete simulation times, and later to start re-simulations from those saved simulation states or design objects states when the visibility is required.
  • the design states of one or more design objects in DUV, which requires the visibility are saved but the states of TB are not saved, then the values on all of inputs and bi-directional input/outs in input mode are saved during the entire simulation period. The saving could be by every event, every cycle, or every transaction.
  • a simulation state is represented by all dynamic and static information of a simulator at the specific simulation time during the execution of simulation.
  • a design state of a design object is represented by the values of all signals and variables in the design object.
  • the design states of a design object can be classified into a complete design state or an incomplete design state, and minimal design state is a special case of incomplete design state.
  • a complete design state of a design object is defined by the values of all signals and variables at a specific simulation time in the design object, and an incomplete design state of a design object is defined by the value(s) of at least one signal or variable at a specific simulation time in the design object.
  • a minimal design state in a design object is defined by the values of all - signals or variables in the design object which represent the outputs of storage elements (flipflops, latches, or memory cells), and if combinational feedback loops exist in the design object, any signals and variables on each loop.
  • a TB state is defined by the values of all variables and signals in TB at a specific simulation time.
  • the simulation When the simulation is resumed from either one of the saved simulation states, or one of the saved design states of design objects in DUV and in some cases one of the saved TB states together (if the design states of the design objects in DUV are saved but the TB states are not saved, then the simulation should be resumed from one of the saved design states of design objects in DUV with the values of all inputs and all bi-directional input/outs in input mode saved in every event, every cycle, or every transaction during the entire simulation period), the dumping on either all signals and variables or some specific signals or variables in the design codes can be carried out during the re- simulation.
  • an example of saving simulation states is to use a simulation system task, save (in case of NC-Verilog, Verilog-XL, or VCS) or checkpoint (in case of ModelSim) command, and an example of re-simulating with a specific simulation state is to use another simulation system task, restore (in case of NC-Verilog, Verilog-XL, or VCS) or restart (in case of ModelSim) command.
  • save in case of NC-Verilog, Verilog-XL, or VCS
  • checkpoint in case of ModelSim
  • re-simulating with a specific simulation state is to use another simulation system task, restore (in case of NC-Verilog, Verilog-XL, or VCS) or restart (in case of ModelSim) command.
  • restore in case of NC-Verilog, Verilog-XL, or VCS
  • restart in case of ModelSim
  • the problem lies in the fact that it is not possible to predict which specific signals or variables in the design are need to be probed at which specific period of simulation time prior to a simulation run. Therefore, it is possible to select some signals or variables to be probed only after a simulation is run at first and its result is evaluated. Then, while the 2 nd simulation is executed from simulation time 0 until the time when the 1 st simulation is terminated, the dump on those selected signals or variables is carried out during a specific simulation period. But, the design error cannot be located at the 2 nd simulation, new signals or variables must be selected for probe and another simulation run needs to be executed from the simulation time 0 again. This process must be repeated many times until the location of the design bug is finally identified.
  • the 1 st simulation run should be executed while dumping all signals and variables in the design code after selecting all of them to be probed before starting the simulation run.
  • the simulation time could be easily increased by the factor of 2 to 10 times or even more if the dumping over all signals and variables in the design code is carried out in the simulation than the simulation time without dumping.
  • the data size of simulation waveform dumped during entire the simulation time for all signals and variables in the design code could be easily exceeded to couples of tens to hundreds of giga-bytes.
  • the simulation technique proposed in the present invention consists of a pair of simulation runs which are divided into front-stage simulation run and back-stage simulation runs.
  • the front-stage simulation run is executed as fast as possible by not to dump all of signals and variables in the design code.
  • Sn are saved at the regular interval (for example, every 100,000 nano-sec or every 50,000 simulation cycles after the simulation run starts) or some specific simulation times tO, t1 tn so that any post-1 st simulation run can begin not from the simulation time 0 but from a simulation time which is very close from the simulation time which users have a concern to watch.
  • the saving of design states of design objects or values on inputs/outputs/inouts can be done by executing some dump commands (for example, some PLI system tasks such as $dumpvars, Sdumports, etc).
  • any post-1 s1 re-simulation run can begin not only from the simulation time 0 but also from any simulation time of tO, t1 tn. Therefore, the debugging for a design can be done quickly and it could be a very efficient verification method as it can reduce the verification time greatly compared to the conventional simulation-based verification methods.
  • Anther method is to use the divide & conquer approach which utilizes the hierarchical structure existed in DUV or TB in a design code.
  • the verification software imports the design code and performs a partition on DUV and TB so that the design code is partitioned into more than one design blocks (let's assume the design code is partitioned into M design blocks), and selects all of inputs and inouts of each partitioned design block as the candidates for probe, and instruments the additional code or design which is responsible for the dumping the selected signals to be probed at the 1 st simulation run, which is the front-stage simulation.
  • the design blocks include both DUV and TB also.
  • Simulation-Method-B instead of producing VCD or FSDB, it is possible to produce one or more TB files directly using VPI/PLI/FLI during the 1 st simulation run. In this case, the translation process from VCD/FSDB into TB could be eliminated.
  • above two techniques can not only provide the high visibility on the design objects without scarifying the simulation speed severely, but also even increase the simulation speed greatly without using any hardware-assisted verification platform(for example, hardware emulator, or FPGA prototyping platform, etc) if the front-stage simulation and the back-stage simulation are executed at different levels of abstraction (will be explained more later). It is also possible to combine both Simulation-Method-A and Simulation-Method-B.
  • Simulation-Method-A can have following problems.
  • Simulation-Method-A if the simulation period at a post-l 51 simulation run, which is back- stage simulation, (ts, te) is quite long, the simulation time could be also long as the total number of n+1 sequential simulation runs are required at ti, ti-1 , ti-2, ..., ti-n times although it could be less than the time required with conventional simulation.
  • simulation-Method-B For Simulation-Method-B, if the number of design blocks to be simulated at a post-1 3 ' simulation run, which is back-stage simulation, (ts, te) is quite many, the simulation time could be also long as many sequential simulation runs are required although it could be less than the time required with conventional simulation. However, if simulators are two or more and the multiple computers, on which the simulators are executed, are connected in a network (for example, the X numbers of simulators are installed on the X numbers of computers), the post-1 5t simulation runs, which is the back-stage simulation, can be done in parallel. As these parallel simulation runs are completely independent with each other, any post-1 st simulation runs can be very fast.
  • First method among them is to execute the 1 st simulation run, which is the front-stage simulation, in parallel also on two or more computers. In this case, as each simulator cannot be run independently with each other, but co-executed together, it is very possible to have significant communication and synchronization overheads.
  • Second method is to simulate with the new code which is translated for faster 1 st simulation from the original code, and has same functionality as the original one but different syntax.
  • the translation is basically to convert some syntax in the original code which takes long simulation time into a new functionally equivalent syntax which can be simulated faster. Eliminating some loop statements by un-rolling the loops, removing unnecessary lists in the sensitivity lists, eliminating the syntax related to delay constructs in some cases, having minimal procedural blocks by combining some of them in Verilog, having minimal processes by combining some of them in VHDL, changing some continuous assignments to procedural assignments and using different sensitivity list from the original for being evaluated less in Verilog, changing some concurrent assignments to processes and using different sensitivity list from the original for being evaluated less in VHDL, changing some continuous assignments to procedural assignments and using sensitivity list being evaluated less in Verilog, changing some concurrent assignments to processes and using sensitivity list from the original for being evaluated less in VHDL, adjusting the sensitivity list in the corresponding always blocks and processes for being evaluated less, and eliminating some signals or variables in the original code which are unnecessary for 1 st simulation are some of those examples.
  • an event-driven simulation is used at the post-1 ⁇ simulation runs, which are the back-stage simulation
  • a cycle-based simulation which is 10 to 100 times faster than the event-driven simulation is used at the 1 st simulation run, which is the front-stage simulation.
  • the original design code written in either Verilog or VHDL can be converted into a SystemC code either manually or automatically (for example using HDL2SystemC translation tool), and a SystemC simulator is used.
  • the event scheduler in the SystemC simulators is very right, it can be run faster than either Verilog or VHDL simulators.
  • TB states all inputs and all bi-directional input/outs in input mode are saved in every event, every cycle, or every transaction during the entire simulation period), are saved at the regular interval or some specific simulation times so that any post-1 ⁇ simulation run can run in parallel with two or more HDL simulators on two or more computers.
  • each sub-simulation in a run of one or more post-1 st simulation runs is executed after initializing its initial state to a design state, which is saved at one or more simulation times at the 1 st simulation run that is the front-stage simulation.
  • the compilation time can be increased due to the increase of file size for TBs, but the elapsed time for running TBs in the simulation run time is reduced as their structure is the form of simple patterns.
  • the technique mentioned above can use the results of RTL simulation using a RTL design code efficiently in the debugging for the gate-level simulation in which the gate-netlist is synthesized from the RTL code, and if necessary the timing information is back-annotated from the placement and routing.
  • the event-driven simulation or cycle-based simulation is used for the first simulation run, which is the front-stage simulation with a RTL design code while saving the design states of the design- code at specific simulation times, then for the one or more- post-1 st simulation as the back-stage simulation the gate-level simulation is carried out in parallel by utilizing those design states of the RTL design code saved at the first simulation.
  • said gate-level simulation could be the timing simulation using SDF(Standard Delay Format), or the functional simulation at the gate level without using any timing information.
  • the post-1 st simulation as the back-stage simulation is using said dynamic information, and if two simulation results of the 1 st simulation and post-1 * simulation are same, then a pair of simulation which uses the different level of abstraction for the 1 st simulation and the post- 1 st simulation (for example, cycle-based simulation at RTL for the 1 st simulation and event-based simulation at RTL for the post-1 A simulation) can run much faster
  • this simulation method is a new verification methodology which can reduce not only the total debugging time, but also the total verification and design time.
  • the advantage is similar to one from the Gain-based Synthesis (GBS), which is using the physical synthesis, proposed by Magma Design Automation, Inc. which had been a big success in the design implementation phase.
  • the 1 s ' verification run which is the front-stage verification, uses one or more simulator(s), simulation accelerator(s), hardware emulator(s), prototyping system(s), formal tools(s) such as model checker(s) or property checker(s), or any combination of those to save the minimal information (for example, the state information of one or more design objects in DUV to be verified at one or more verification times, and if necessary, values of all inputs and inouts in input mode of said design objects during the entire verification period) which requires to execute at the post-1 st verification runs, which is the back-stage verification, with one or more simulator(s), simulation accelerator(s), hardware emulator(s), prototyping system(s), formal tools(s) such as model checker(s) or property checker(s), or any combination of those in either sequential or parallel.
  • the minimal information for example, the state information of one or more design objects in DUV to be verified at one or more verification times, and if necessary, values of all inputs and inouts in input mode of said design objects during
  • the reuse could be applied in the case of regression testing, which is needed whenever there is any design modification during the debugging, and the case of assuring the correctness of modification after the design object has been modified.
  • a verification run is not carried out with the entire design object (including both DUV and TB). Instead, during one or more specific verification periods (for example, from the verification time 0 to tm), one or more design objects which are modified, DO(mod) only are executed at faster speed, and during remaining verification times (for' example, after tm) the entire DUV and TB are executed.
  • the critical element for this method is to identify one or more periods in which only one or more design objects, that are modified, can be executed.
  • DO(mod) modified design objects
  • FIG. 1 is an example of the schematic view of the design verification apparatus in accordance with the present invention.
  • FIG. 2 is another example of the schematic view of the design verification apparatus in accordance with the present invention.
  • FIG. 3 is a schematic view of a simulation process by the method proposed in the present invention.
  • FIG. 4 is a schematic view of a bug finding and removing process throughout the simulation proposed in the present invention, which consists of the 1 st simulation as the front-stage simulation and the post-1 st simulations as the back-stage simulation.
  • FIG. 5(a) is a schematic view showing a verification process in the verification using the apparatus showing in FIG. 1 or FIG. 2.
  • FIG. 5(b) is a schematic view showing another verification process in the verification using the apparatus showing in FIG. 1 or FIG. 2.
  • FIG. 6(a) is a schematic view showing a verification process in which the post-1 st simulations as the back-stage simulation are executed in parallel, using the verification apparatus in FIG. 2.
  • FIG. 5(a) is a schematic view showing a verification process in which the post-1 st simulations as the back-stage simulation are executed in parallel, using the verification apparatus in FIG. 2.
  • FIG. 5(a) is a schematic view
  • FIG. 6(b) is a schematic view showing another verification process, in which the post-1 st simulations as the back-stage simulation are executed in parallel, using the verification apparatus in FIG. 2.
  • FIG. 6(c) is a schematic view showing another verification process, in which the post-1 st simulations as the back-stage simulation are executed in parallel, using the verification apparatus in FIG. 2.
  • FIG. 6(d) is a schematic view showing another verification process, in which the post-1 st simulations as the back-stage simulation are executed in parallel, using the verification apparatus in FIG. 2.
  • FIG. 7 is another example of the schematic view of the design verification apparatus in accordance with the present invention.
  • FIG. 8 is an example of the schematic view of the design verification apparatus in accordance with the present invention which consists of verification software of the present invention, at least one computer having at least one simulator, and at least one hardware-assisted verification platform.
  • FIG. 9 is an example of the schematic view of the design verification apparatus in accordance with the present invention which consists of verification software of the present invention, at least two computers having at least two simulators, at least one hardware-assisted verification platform, and a computer network which connects among them.
  • FIG. 10 is an another example of the schematic view of the design verification apparatus in accordance with the present invention which consists of verification software of the present invention, at least one computer having at least one simulator, and at least one hardware-assisted verification platform.
  • FIG 11 is an example of the schematic view showing the reuse of the previous verification results in the verification using the apparatus in FIG. 8.
  • FIG. 12 is an example of the schematic view showing the reuse of the previous simulation results in the verification using the apparatus in FIG. 1.
  • FIG. 13 is an example of the schematic view showing the fast execution of verification process by re-using the verification results of any design objects unaltered on an arbitrary verification platform after some design objects are modified.
  • FIG. 14 is an example of the schematic view showing the fast execution of verification process by re-using the verification results of any design objects unaltered on an arbitrary hardware-assisted verification platform after some design objects are modified.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

L'invention porte sur un appareil et sur un procédé de vérification basés sur la simulation, qui permettent d'améliorer dans une large mesure la performance et l'efficacité de la simulation, et de vérifier un système numérique comprenant au moins un million de portes. L'invention concerne également un appareil et un procédé de vérification basés sur la simulation qui permettent d'effectuer une vérification formelle, d'accélérer la simulation, d'émuler le matériel et de réaliser un prototypage présentant une performance et une efficacité de vérification élevées afin de vérifier un système numérique comprenant au moins un million de portes.
PCT/KR2005/000668 2004-03-09 2005-03-09 Appareil de verification dynamique permettant d'obtenir une performance et une efficacite de verification elevees et procede de verification associe WO2005093575A1 (fr)

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US10/591,910 US20080306721A1 (en) 2004-03-09 2005-03-09 Dynamic-Verification-Based Verification Apparatus Achieving High Verification Performance and Verification Efficiency and the Verification Methodology Using the Same
JP2007502715A JP2007528553A (ja) 2004-03-09 2005-03-09 検証性能と検証效率性を高める動的検証−基盤方式の検証装置及びこれを用いた検証方法論

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KR10-2004-0017476 2004-03-09
KR1020040017476A KR20040063845A (ko) 2001-09-14 2004-03-09 검증 성능을 높이는 시뮬레이션 기반의 검증 장치 및 이를이용한 시뮬레이션 방법
KR10-2004-0019066 2004-03-16
KR1020040019066A KR20040063846A (ko) 2001-09-14 2004-03-16 다양한 검증 플랫폼들의 통합 사용을 지원하는 검증 장치및 이를 이용한 검증 방법
KR10-2004-0055329 2004-07-12
KR20040055329 2004-07-12
KR1020040093309A KR20050090053A (ko) 2004-03-06 2004-11-08 검증 성능을 높이는 시뮬레이션 기반의 검증 장치 및 이를이용한 시뮬레이션 방법
KR10-2004-0093309 2004-11-08
KR1020050007330A KR20050118107A (ko) 2004-03-09 2005-01-24 검증 성능과 검증 효율성을 높이는 동적검증 기법 방식의검증 장치 및 이를 이용한 검증 방법론
KR10-2005-0007330 2005-01-24

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US8781808B2 (en) 2005-10-10 2014-07-15 Sei Yang Yang Prediction-based distributed parallel simulation method
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US10061876B2 (en) 2014-12-23 2018-08-28 Board Of Trustees Of The University Of Illinois Bounded verification through discrepancy computations
CN109726507A (zh) * 2019-01-17 2019-05-07 湖南进芯电子科技有限公司 一种高效的多功能验证平台及方法
CN111310396A (zh) * 2020-02-13 2020-06-19 深圳航天科技创新研究院 一种fpga虚拟平台及实现fpga虚拟平台的方法

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JP6352607B2 (ja) * 2012-09-07 2018-07-04 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． アサーション生成装置及び方法並びにプロセッサ検証装置及び方法

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