CA2110472C - Method and apparatus for in-situ testing of integrated circuit chips - Google Patents

Method and apparatus for in-situ testing of integrated circuit chips

Info

Publication number
CA2110472C
CA2110472C CA002110472A CA2110472A CA2110472C CA 2110472 C CA2110472 C CA 2110472C CA 002110472 A CA002110472 A CA 002110472A CA 2110472 A CA2110472 A CA 2110472A CA 2110472 C CA2110472 C CA 2110472C
Authority
CA
Canada
Prior art keywords
chip
chips
contacts
dendrites
testing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002110472A
Other languages
English (en)
French (fr)
Other versions
CA2110472A1 (en
Inventor
Anilkumar Chinuprasad Bhatt
Leo Raymond Buda
Robert Douglas Edwards
Paul Joseph Hart
Anthony Paul Ingraham
Voya Rista Markovich
Jaynal Abedin Molla
Richard Gerald Murphy
George John Saxenmeyer, Jr.
George Frederick Walker
Bette Jaye Whalen
Richard Stuart Zarr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2110472A1 publication Critical patent/CA2110472A1/en
Application granted granted Critical
Publication of CA2110472C publication Critical patent/CA2110472C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2879—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/01—Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
    • H10P74/23—
    • H10W72/0711—
    • H10W72/07236—
    • H10W72/252—
    • H10W72/29—
    • H10W72/934—

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Environmental & Geological Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
CA002110472A 1993-03-01 1993-12-01 Method and apparatus for in-situ testing of integrated circuit chips Expired - Fee Related CA2110472C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2454993A 1993-03-01 1993-03-01
US024,549 1993-03-01

Publications (2)

Publication Number Publication Date
CA2110472A1 CA2110472A1 (en) 1994-09-02
CA2110472C true CA2110472C (en) 1999-08-10

Family

ID=21821176

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002110472A Expired - Fee Related CA2110472C (en) 1993-03-01 1993-12-01 Method and apparatus for in-situ testing of integrated circuit chips

Country Status (6)

Country Link
US (1) US6414509B1 (OSRAM)
EP (1) EP0614089A3 (OSRAM)
JP (1) JP2528619B2 (OSRAM)
KR (1) KR0130736B1 (OSRAM)
CA (1) CA2110472C (OSRAM)
TW (1) TW232090B (OSRAM)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5829128A (en) 1993-11-16 1998-11-03 Formfactor, Inc. Method of mounting resilient contact structures to semiconductor devices
US5917707A (en) 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
US5476211A (en) 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
US7084656B1 (en) 1993-11-16 2006-08-01 Formfactor, Inc. Probe for semiconductor devices
US7200930B2 (en) 1994-11-15 2007-04-10 Formfactor, Inc. Probe for semiconductor devices
WO1996015459A1 (en) * 1994-11-15 1996-05-23 Formfactor, Inc. Mounting spring elements on semiconductor devices, and wafer-level testing methodology
DE69530103T2 (de) * 1994-11-15 2003-12-11 Formfactor, Inc. Verbindungselemente für mikroelektronische komponenten
US20100065963A1 (en) 1995-05-26 2010-03-18 Formfactor, Inc. Method of wirebonding that utilizes a gas flow within a capillary from which a wire is played out
US6142789A (en) * 1997-09-22 2000-11-07 Silicon Graphics, Inc. Demateable, compliant, area array interconnect
US7898275B1 (en) * 1997-10-03 2011-03-01 Texas Instruments Incorporated Known good die using existing process infrastructure
JP3553791B2 (ja) 1998-04-03 2004-08-11 株式会社ルネサステクノロジ 接続装置およびその製造方法、検査装置並びに半導体素子の製造方法
DE10127351A1 (de) * 2001-06-06 2002-12-19 Infineon Technologies Ag Elektronischer Chip und elektronische Chip-Anordnung
US6764869B2 (en) * 2001-09-12 2004-07-20 Formfactor, Inc. Method of assembling and testing an electronics module
US6747472B2 (en) * 2002-01-18 2004-06-08 International Business Machines Corporation Temporary device attach structure for test and burn in of microjoint interconnects and method for fabricating the same
US6836134B2 (en) * 2002-06-11 2004-12-28 Delphi Technologies, Inc. Apparatus and method for determining leakage current between a first semiconductor region and a second semiconductor region to be formed therein
CN101523550B (zh) * 2006-09-12 2011-06-15 皇家飞利浦电子股份有限公司 包括嵌入在灯的石英玻璃封壳中的导体的灯
US8262768B2 (en) 2007-09-17 2012-09-11 Barrick Gold Corporation Method to improve recovery of gold from double refractory gold ores
EA020884B1 (ru) 2007-09-18 2015-02-27 Баррик Гольд Корпорейшн Способ восстановления золота из тугоплавких сульфидных руд
US8262770B2 (en) 2007-09-18 2012-09-11 Barrick Gold Corporation Process for controlling acid in sulfide pressure oxidation processes
US9104568B2 (en) 2013-03-15 2015-08-11 International Business Machines Corporation Detection of memory cells that are stuck in a physical state
CN113990793A (zh) * 2021-10-21 2022-01-28 东莞市中麒光电技术有限公司 一种led芯片转移方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4189825A (en) * 1975-06-04 1980-02-26 Raytheon Company Integrated test and assembly device
US4328286A (en) 1979-04-26 1982-05-04 The International Nickel Co., Inc. Electrodeposited palladium, method of preparation and electrical contact made thereby
JPS57110690A (en) 1980-12-24 1982-07-09 Ibm Growing of tentrite by electroplating
US4716124A (en) 1984-06-04 1987-12-29 General Electric Company Tape automated manufacture of power semiconductor devices
US4820976A (en) 1987-11-24 1989-04-11 Advanced Micro Devices, Inc. Test fixture capable of electrically testing an integrated circuit die having a planar array of contacts
DE68913823T2 (de) * 1988-06-21 1994-09-22 Ibm Lösbare elektrische Verbindung.
US5137461A (en) * 1988-06-21 1992-08-11 International Business Machines Corporation Separable electrical connection technology
US5007163A (en) * 1990-04-18 1991-04-16 International Business Machines Corporation Non-destructure method of performing electrical burn-in testing of semiconductor chips
US5118299A (en) * 1990-05-07 1992-06-02 International Business Machines Corporation Cone electrical contact
GB2247565B (en) * 1990-08-22 1994-07-06 Gen Electric Co Plc A method of testing a semiconductor device
US5088190A (en) * 1990-08-30 1992-02-18 Texas Instruments Incorporated Method of forming an apparatus for burn in testing of integrated circuit chip
US5237269A (en) * 1991-03-27 1993-08-17 International Business Machines Corporation Connections between circuit chips and a temporary carrier for use in burn-in tests
US5420520A (en) * 1993-06-11 1995-05-30 International Business Machines Corporation Method and apparatus for testing of integrated circuit chips
US5523696A (en) * 1993-06-14 1996-06-04 International Business Machines Corp. Method and apparatus for testing integrated circuit chips
US5659256A (en) * 1993-06-11 1997-08-19 International Business Machines Corporation Method and apparatus for testing integrated circuit chips
US5494856A (en) * 1994-10-18 1996-02-27 International Business Machines Corporation Apparatus and method for creating detachable solder connections
US6037786A (en) * 1996-12-13 2000-03-14 International Business Machines Corporation Testing integrated circuit chips

Also Published As

Publication number Publication date
JPH06252226A (ja) 1994-09-09
EP0614089A3 (en) 1995-07-12
EP0614089A2 (en) 1994-09-07
US6414509B1 (en) 2002-07-02
TW232090B (OSRAM) 1994-10-11
KR940022769A (ko) 1994-10-21
JP2528619B2 (ja) 1996-08-28
CA2110472A1 (en) 1994-09-02
KR0130736B1 (ko) 1998-04-06

Similar Documents

Publication Publication Date Title
US5420520A (en) Method and apparatus for testing of integrated circuit chips
CA2110472C (en) Method and apparatus for in-situ testing of integrated circuit chips
US5528159A (en) Method and apparatus for testing integrated circuit chips
US5007163A (en) Non-destructure method of performing electrical burn-in testing of semiconductor chips
US6118138A (en) Reduced terminal testing system
US6233184B1 (en) Structures for wafer level test and burn-in
US5659256A (en) Method and apparatus for testing integrated circuit chips
US5831445A (en) Wafer scale burn-in apparatus and process
US6822469B1 (en) Method for testing multiple semiconductor wafers
US5686843A (en) Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module
US4920454A (en) Wafer scale package system and header and method of manufacture thereof
US5239199A (en) Vertical lead-on-chip package
EP0802418A2 (en) Method for high-speed testing a semiconductor device
US5461544A (en) Structure and method for connecting leads from multiple chips
EP0495629B1 (en) Vertical lead-on-chip package
KR100460471B1 (ko) 웨이퍼 레벨 번-인 공정 및 시험
KR100460470B1 (ko) 웨이퍼레벨번-인공정및시험
JPH04106959A (ja) 多面付チップキャリア基板のプッシュバック工法
Quinn et al. New Process for Automated IC Assembly Manufacturing
JPH07118495B2 (ja) フィルムキャリアテープ
JPS60226140A (ja) 半導体集積回路装置
JPS63114246A (ja) 半導体装置
JPH0815175B2 (ja) 高密度多層配線基板実装構造

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed