CA2048206A1 - Mis electrodes forming process - Google Patents

Mis electrodes forming process

Info

Publication number
CA2048206A1
CA2048206A1 CA002048206A CA2048206A CA2048206A1 CA 2048206 A1 CA2048206 A1 CA 2048206A1 CA 002048206 A CA002048206 A CA 002048206A CA 2048206 A CA2048206 A CA 2048206A CA 2048206 A1 CA2048206 A1 CA 2048206A1
Authority
CA
Canada
Prior art keywords
forming
insulation film
mis
substrate
iii
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002048206A
Other languages
English (en)
French (fr)
Inventor
Shin-Ichi Shikata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2204531A external-priority patent/JPH0491436A/ja
Priority claimed from JP2204529A external-priority patent/JPH0491435A/ja
Application filed by Individual filed Critical Individual
Publication of CA2048206A1 publication Critical patent/CA2048206A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28264—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CA002048206A 1990-08-01 1991-07-31 Mis electrodes forming process Abandoned CA2048206A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP204529/1990 1990-08-01
JP204531/1990 1990-08-01
JP2204531A JPH0491436A (ja) 1990-08-01 1990-08-01 Ｍｉｓ構造電極の形成方法
JP2204529A JPH0491435A (ja) 1990-08-01 1990-08-01 Ｍｉｓ構造電極の形成方法

Publications (1)

Publication Number Publication Date
CA2048206A1 true CA2048206A1 (en) 1992-02-02

Family

ID=26514514

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002048206A Abandoned CA2048206A1 (en) 1990-08-01 1991-07-31 Mis electrodes forming process

Country Status (4)

Country Link
US (1) US5393680A (cs)
EP (1) EP0469604A2 (cs)
KR (1) KR950007956B1 (cs)
CA (1) CA2048206A1 (cs)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5393680A (en) * 1990-08-01 1995-02-28 Sumitomo Electric Industries, Ltd. MIS electrode forming process
JP3578539B2 (ja) * 1996-02-08 2004-10-20 三菱電機株式会社 太陽電池の製造方法および太陽電池構造
US6207976B1 (en) * 1997-12-17 2001-03-27 Fujitsu Limited Semiconductor device with ohmic contacts on compound semiconductor and manufacture thereof
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US8183556B2 (en) 2005-12-15 2012-05-22 Intel Corporation Extreme high mobility CMOS logic
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
EP2187432B1 (en) * 2008-11-13 2013-01-09 Epcos AG P-type field-effect transistor and method of production
KR20120049899A (ko) 2009-09-04 2012-05-17 스미또모 가가꾸 가부시키가이샤 반도체 기판, 전계 효과 트랜지스터, 집적 회로 및 반도체 기판의 제조 방법
KR101867999B1 (ko) * 2011-10-31 2018-06-18 삼성전자주식회사 Ｉｉｉ-ｖ족 물질층을 형성하는 방법, ｉｉｉ-ｖ족 물질층을 포함하는 반도체 소자 및 그 제조방법
US9478419B2 (en) 2013-12-18 2016-10-25 Asm Ip Holding B.V. Sulfur-containing thin films
US9245742B2 (en) 2013-12-18 2016-01-26 Asm Ip Holding B.V. Sulfur-containing thin films
US9461134B1 (en) 2015-05-20 2016-10-04 Asm Ip Holding B.V. Method for forming source/drain contact structure with chalcogen passivation
US10490475B2 (en) 2015-06-03 2019-11-26 Asm Ip Holding B.V. Methods for semiconductor passivation by nitridation after oxide removal
US9711350B2 (en) 2015-06-03 2017-07-18 Asm Ip Holding B.V. Methods for semiconductor passivation by nitridation
US9711396B2 (en) 2015-06-16 2017-07-18 Asm Ip Holding B.V. Method for forming metal chalcogenide thin films on a semiconductor device
US9741815B2 (en) 2015-06-16 2017-08-22 Asm Ip Holding B.V. Metal selenide and metal telluride thin films for semiconductor device applications

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2454184A1 (fr) * 1979-04-10 1980-11-07 Chemla Daniel Structure de type isolant-semi-conducteur dans laquelle le semi-conducteur est un compose iii-v et l'isolant un sulfure, et procedes de fabrication de cette structure
US4467521A (en) * 1983-08-15 1984-08-28 Sperry Corporation Selective epitaxial growth of gallium arsenide with selective orientation
JPS6231170A (ja) * 1985-08-02 1987-02-10 Agency Of Ind Science & Technol 化合物半導体装置の構造
JPS6294944A (ja) * 1985-10-21 1987-05-01 Nec Corp ３−５化合物半導体のｍｉｓ構造形成方法
FR2604826B1 (fr) * 1986-10-06 1989-01-20 France Etat Procede de formation d'une couche isolante comportant du sulfure, derives sulfures obtenus et appareillage pour la mise en oeuvre du procede
US4751200A (en) * 1987-03-04 1988-06-14 Bell Communications Research, Inc. Passivation of gallium arsenide surfaces with sodium sulfide
US4751201A (en) * 1987-03-04 1988-06-14 Bell Communications Research, Inc. Passivation of gallium arsenide devices with sodium sulfide
US4871692A (en) * 1988-09-30 1989-10-03 Lee Hong H Passivation of group III-V surfaces
JP2681117B2 (ja) * 1989-04-26 1997-11-26 康夫 南日 化合物半導体表面の安定化方法
US4920078A (en) * 1989-06-02 1990-04-24 Bell Communications Research, Inc. Arsenic sulfide surface passivation of III-V semiconductors
JPH0311633A (ja) * 1989-06-08 1991-01-18 Sekiyu Sangyo Katsuseika Center 化合物半導体装置の製造方法
JP2841775B2 (ja) * 1990-08-01 1998-12-24 住友電気工業株式会社 半導体レーザの保護膜形成方法
JP2830414B2 (ja) * 1990-08-01 1998-12-02 住友電気工業株式会社 Ｍｅｓ構造電極の形成方法
US5393680A (en) * 1990-08-01 1995-02-28 Sumitomo Electric Industries, Ltd. MIS electrode forming process

Also Published As

Publication number Publication date
KR950007956B1 (ko) 1995-07-21
EP0469604A2 (en) 1992-02-05
EP0469604A3 (cs) 1995-02-01
US5393680A (en) 1995-02-28

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Legal Events

Date Code Title Description
FZDE Discontinued