CA2037142A1 - Structure et circuits logiques de report rapide - Google Patents

Structure et circuits logiques de report rapide

Info

Publication number
CA2037142A1
CA2037142A1 CA 2037142 CA2037142A CA2037142A1 CA 2037142 A1 CA2037142 A1 CA 2037142A1 CA 2037142 CA2037142 CA 2037142 CA 2037142 A CA2037142 A CA 2037142A CA 2037142 A1 CA2037142 A1 CA 2037142A1
Authority
CA
Canada
Prior art keywords
bits
carry
function
added
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA 2037142
Other languages
English (en)
Other versions
CA2037142C (fr
Inventor
Hung-Cheng Hsieh
William S. Carter
Charles R. Erickson
Edmond Y. Cheung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of CA2037142A1 publication Critical patent/CA2037142A1/fr
Application granted granted Critical
Publication of CA2037142C publication Critical patent/CA2037142C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5057—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using table look-up; using programmable logic arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Complex Calculations (AREA)
CA 2037142 1990-05-10 1991-02-26 Structure et circuits logiques de report rapide Expired - Fee Related CA2037142C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US52233690A 1990-05-10 1990-05-10
US07/522,336 1990-05-10

Publications (2)

Publication Number Publication Date
CA2037142A1 true CA2037142A1 (fr) 1991-11-11
CA2037142C CA2037142C (fr) 1996-05-07

Family

ID=24080466

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2037142 Expired - Fee Related CA2037142C (fr) 1990-05-10 1991-02-26 Structure et circuits logiques de report rapide

Country Status (4)

Country Link
EP (2) EP1046982B1 (fr)
JP (1) JPH0766320B2 (fr)
CA (1) CA2037142C (fr)
DE (2) DE69132540T2 (fr)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5322812A (en) 1991-03-20 1994-06-21 Crosspoint Solutions, Inc. Improved method of fabricating antifuses in an integrated circuit device and resulting structure
US5633830A (en) * 1995-11-08 1997-05-27 Altera Corporation Random access memory block circuitry for programmable logic array integrated circuit devices
US5274581A (en) * 1992-05-08 1993-12-28 Altera Corporation Look up table implementation of fast carry for adders and counters
USRE35977E (en) * 1992-05-08 1998-12-01 Altera Corporation Look up table implementation of fast carry arithmetic and exclusive-or operations
US5349250A (en) * 1993-09-02 1994-09-20 Xilinx, Inc. Logic structure and circuit for fast carry
US6154053A (en) * 1993-09-02 2000-11-28 Xilinx, Inc. Look-ahead carry structure with homogeneous CLB structure and pitch larger than CLB pitch
US6288570B1 (en) 1993-09-02 2001-09-11 Xilinx, Inc. Logic structure and circuit for fast carry
US5898319A (en) * 1993-09-02 1999-04-27 Xilinx, Inc. Method and structure for providing fast conditional sum in a field programmable gate array
US5629886A (en) * 1993-09-02 1997-05-13 Xilinx, Inc. Method and structure for providing fast propagation of a carry signal in a field programmable gate array
US5546018A (en) * 1993-09-02 1996-08-13 Xilinx, Inc. Fast carry structure with synchronous input
GB2317248B (en) 1996-09-02 2001-08-15 Siemens Plc Floating point number data processing means
US5966029A (en) * 1997-07-15 1999-10-12 Motorola, Inc. Multi-bit exclusive or
JP4852149B2 (ja) * 2007-05-21 2012-01-11 ルネサスエレクトロニクス株式会社 半導体装置
RU2503993C1 (ru) * 2012-04-26 2014-01-10 федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Пермский национальный исследовательский политехнический университет" Программируемое логическое устройство
RU2573732C2 (ru) * 2014-02-25 2016-01-27 Сергей Феофентович Тюрин Программируемое логическое устройство
RU2602780C2 (ru) * 2014-04-17 2016-11-20 Сергей Феофентович Тюрин Программируемое логическое устройство
RU2573758C2 (ru) * 2014-04-25 2016-01-27 Сергей Феофентович Тюрин Программируемое логическое устройство
RU2547229C1 (ru) * 2014-05-21 2015-04-10 федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Пермский национальный исследовательский политехнический университет" Программируемое логическое устройство
RU2544750C1 (ru) * 2014-05-22 2015-03-20 федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Пермский национальный исследовательский политехнический университет" Программируемое логическое устройство

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5841533B2 (ja) * 1975-10-31 1983-09-13 日本電気株式会社 ゼンカゲンサンカイロ
US4218747A (en) * 1978-06-05 1980-08-19 Fujitsu Limited Arithmetic and logic unit using basic cells
EP0098692A3 (fr) * 1982-07-01 1986-04-16 Hewlett-Packard Company Dispositif d'addition d'un premier et d'un second opérandes binaires
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4706216A (en) * 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
JPS6270935A (ja) * 1985-09-24 1987-04-01 Sharp Corp デイジタル加算器
US4758745B1 (en) * 1986-09-19 1994-11-15 Actel Corp User programmable integrated circuit interconnect architecture and test method
JPH01180633A (ja) * 1988-01-12 1989-07-18 Mitsubishi Electric Corp 加算器
JPH01181127A (ja) * 1988-01-14 1989-07-19 Fujitsu Ltd 並列形全加算器
EP0333884B1 (fr) * 1988-03-19 1994-06-08 Deutsche ITT Industries GmbH Circuit multiplieur parallèle-série ainsi que ses étages de multiplication et d'addition

Also Published As

Publication number Publication date
DE69132540T2 (de) 2001-07-05
JPH0766320B2 (ja) 1995-07-19
DE69133327D1 (de) 2003-11-13
EP0456475A2 (fr) 1991-11-13
JPH04242825A (ja) 1992-08-31
EP0456475A3 (en) 1993-02-24
EP1046982A2 (fr) 2000-10-25
EP1046982B1 (fr) 2003-10-08
CA2037142C (fr) 1996-05-07
EP0456475B1 (fr) 2001-02-28
DE69132540D1 (de) 2001-04-05
DE69133327T2 (de) 2004-08-05
EP1046982A3 (fr) 2000-11-02

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