CA2008228A1 - Circuit d'ajustement de phase - Google Patents
Circuit d'ajustement de phaseInfo
- Publication number
- CA2008228A1 CA2008228A1 CA2008228A CA2008228A CA2008228A1 CA 2008228 A1 CA2008228 A1 CA 2008228A1 CA 2008228 A CA2008228 A CA 2008228A CA 2008228 A CA2008228 A CA 2008228A CA 2008228 A1 CA2008228 A1 CA 2008228A1
- Authority
- CA
- Canada
- Prior art keywords
- adjustment circuit
- phase adjustment
- high speed
- master
- frame pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003111 delayed effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP01-009906 | 1989-01-20 | ||
JP1009906A JPH02192337A (ja) | 1989-01-20 | 1989-01-20 | 位相調整回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2008228A1 true CA2008228A1 (fr) | 1990-07-20 |
CA2008228C CA2008228C (fr) | 1995-01-31 |
Family
ID=11733156
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002008228A Expired - Fee Related CA2008228C (fr) | 1989-01-20 | 1990-01-22 | Circuit d'ajustement de phase |
Country Status (5)
Country | Link |
---|---|
US (1) | US5051990A (fr) |
EP (1) | EP0379384B1 (fr) |
JP (1) | JPH02192337A (fr) |
CA (1) | CA2008228C (fr) |
DE (1) | DE69018103T2 (fr) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3120994B2 (ja) * | 1990-05-11 | 2000-12-25 | キヤノン株式会社 | デジタル交換装置 |
JPH04175028A (ja) * | 1990-07-23 | 1992-06-23 | Fujitsu Ltd | 多チャネル接続装置の伝送路インタフェース回路 |
US5163068A (en) * | 1991-02-22 | 1992-11-10 | El Amawy Ahmed | Arbitrarily large clock networks with constant skew bound |
JPH0548560A (ja) * | 1991-08-16 | 1993-02-26 | Fujitsu Ltd | Pcm伝送路におけるデータのフレーム遅延補正方式 |
US5522088A (en) * | 1994-06-17 | 1996-05-28 | International Business Machines Corporation | Shared channel subsystem has a self timed interface using a received clock signal to individually phase align bits received from a parallel bus |
US6192482B1 (en) | 1994-06-17 | 2001-02-20 | International Business Machines Corporation | Self-timed parallel data bus interface to direct storage devices |
EP0687986A3 (fr) * | 1994-06-17 | 1996-02-14 | Ibm | Méthode et appareil pour la transmission de données digitales dans des systèmes massivement parallèles |
US5513377A (en) * | 1994-06-17 | 1996-04-30 | International Business Machines Corporation | Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus |
US5832047A (en) * | 1994-06-17 | 1998-11-03 | International Business Machines Corporation | Self timed interface |
US5598442A (en) * | 1994-06-17 | 1997-01-28 | International Business Machines Corporation | Self-timed parallel inter-system data communication channel |
JP3203978B2 (ja) * | 1994-07-25 | 2001-09-04 | ソニー株式会社 | データ送受信装置、データ受信装置及びデータ送信装置 |
JP3468592B2 (ja) * | 1994-08-10 | 2003-11-17 | 富士通株式会社 | クロック信号発生回路 |
KR0177733B1 (ko) * | 1994-08-26 | 1999-05-15 | 정장호 | 데이타 전송장치의 클럭동기 회로 |
US5550875A (en) * | 1994-12-29 | 1996-08-27 | Unisys Corporation | Apparatus and method for residual error clock skew bound, and clocking therewith |
US20070268839A1 (en) * | 2006-05-16 | 2007-11-22 | Shane Keating | Method and apparatus for autoconfiguring a high speed serial port |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3708783A (en) * | 1971-06-18 | 1973-01-02 | Ampex | Interchannel time displacement correction method and apparatus |
US3909541A (en) * | 1974-03-11 | 1975-09-30 | Bell Telephone Labor Inc | Low-speed framing arrangement for a high-speed digital bitstream |
DE2837214A1 (de) * | 1978-08-25 | 1980-03-06 | Siemens Ag | Anordnung zum uebertragen von digitalen datensignalen |
JPS5760754A (en) * | 1980-09-27 | 1982-04-12 | Fujitsu Ltd | Synchronizing circuit |
US4451917A (en) * | 1981-01-15 | 1984-05-29 | Lynch Communication Systems, Inc. | Method and apparatus for pulse train synchronization in PCM transceivers |
US4694472A (en) * | 1982-04-26 | 1987-09-15 | American Telephone And Telegraph Company | Clock adjustment method and apparatus for synchronous data communications |
US4805195A (en) * | 1984-06-08 | 1989-02-14 | Amdahl Corporation | Selectable timing delay circuit |
US4630286A (en) * | 1984-10-10 | 1986-12-16 | Paradyne Corporation | Device for synchronization of multiple telephone circuits |
FR2601534B1 (fr) * | 1986-07-10 | 1993-07-30 | Cit Alcatel | Procede et dispositif de calage en phase de trains numeriques synchrones |
US4805196A (en) * | 1987-04-29 | 1989-02-14 | Gte Laboratories Incorporated | Line delay compensation for digital transmission systems utilizing low power line drivers |
-
1989
- 1989-01-20 JP JP1009906A patent/JPH02192337A/ja active Pending
-
1990
- 1990-01-19 DE DE69018103T patent/DE69018103T2/de not_active Expired - Fee Related
- 1990-01-19 EP EP90300575A patent/EP0379384B1/fr not_active Expired - Lifetime
- 1990-01-22 US US07/468,284 patent/US5051990A/en not_active Expired - Lifetime
- 1990-01-22 CA CA002008228A patent/CA2008228C/fr not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69018103T2 (de) | 1995-08-03 |
EP0379384B1 (fr) | 1995-03-29 |
CA2008228C (fr) | 1995-01-31 |
EP0379384A2 (fr) | 1990-07-25 |
US5051990A (en) | 1991-09-24 |
EP0379384A3 (fr) | 1991-11-06 |
DE69018103D1 (de) | 1995-05-04 |
JPH02192337A (ja) | 1990-07-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA2008228A1 (fr) | Circuit d'ajustement de phase | |
HUT56265A (en) | Process for producing fine-dispersing, solid, crystalline powders by precipitation into nonsolving medium | |
AU1437292A (en) | Antiviral 1,3-dioxolane nucleosides and synthesis thereof | |
EP0615212A3 (fr) | Méthode de traitement de courrier à grande vitesse. | |
GB2260838B (en) | Data output buffers | |
AU2295483A (en) | Pulse radar apparatus | |
AU8940391A (en) | Selenium removal process | |
AU1357888A (en) | Method for producing fruit chips | |
AU618160B2 (en) | Data delay circuit and clock extraction circuit using the same | |
AU1713483A (en) | 5-oxo-2,3,6,7-tetrahydro-5h-thiazolo(3,2-alpha)pyrimidine derivatives | |
AU1676883A (en) | Synchrononus clock pulse generator | |
HUT58700A (en) | Process for producing dialkyl-pyridine-2,3-dicarboxylate and derivatives from dialkyl-dichloro-mateate | |
AU601132B2 (en) | Variable bit rate clock recovery circuit | |
AU1357988A (en) | Method for producing fruit chips | |
AU4498389A (en) | Method for producing chitosan | |
AU5749390A (en) | Method and circuit for generating dependent clock signals | |
AU4409689A (en) | Amidofluoranited compounds, method for producing and using said compounds | |
AU646375B2 (en) | Phase locked loop for extracting clock pulses through wave differential method | |
DE68913919D1 (de) | Hochfrequenz-Taktimpulszähler. | |
HU9202929D0 (en) | Substituted amino-propane derivatives, method for producing them and their utilization | |
AU2376684A (en) | 5-oxo-2,4-dichloro-4-substituted pentanenitriles | |
AU2701784A (en) | Pulse radar apparatus | |
JPS546424A (en) | Signal processing method of solid pickup unit | |
CA2050656A1 (fr) | Systeme numerique de radiotransmission de donnees | |
CA2031934A1 (fr) | Circuit a inertie |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |