CA1142275A - Self-aligned method for making bipolar transistor having minimum base to emitter contact spacing - Google Patents

Self-aligned method for making bipolar transistor having minimum base to emitter contact spacing

Info

Publication number
CA1142275A
CA1142275A CA000365461A CA365461A CA1142275A CA 1142275 A CA1142275 A CA 1142275A CA 000365461 A CA000365461 A CA 000365461A CA 365461 A CA365461 A CA 365461A CA 1142275 A CA1142275 A CA 1142275A
Authority
CA
Canada
Prior art keywords
mesas
substrate
emitter
method described
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000365461A
Other languages
English (en)
French (fr)
Inventor
Harsaran S. Bhatia
James L. Walsh
Narasipur G. Anantha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1142275A publication Critical patent/CA1142275A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/141—Self-alignment coat gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
CA000365461A 1980-01-25 1980-11-25 Self-aligned method for making bipolar transistor having minimum base to emitter contact spacing Expired CA1142275A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US115,307 1980-01-25
US06/115,307 US4252582A (en) 1980-01-25 1980-01-25 Self aligned method for making bipolar transistor having minimum base to emitter contact spacing

Publications (1)

Publication Number Publication Date
CA1142275A true CA1142275A (en) 1983-03-01

Family

ID=22360518

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000365461A Expired CA1142275A (en) 1980-01-25 1980-11-25 Self-aligned method for making bipolar transistor having minimum base to emitter contact spacing

Country Status (5)

Country Link
US (1) US4252582A (OSRAM)
EP (1) EP0032999B1 (OSRAM)
JP (1) JPS56110261A (OSRAM)
CA (1) CA1142275A (OSRAM)
DE (1) DE3070658D1 (OSRAM)

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US4425574A (en) 1979-06-29 1984-01-10 International Business Machines Corporation Buried injector memory cell formed from vertical complementary bipolar transistor circuits and method of fabrication therefor
US4309812A (en) * 1980-03-03 1982-01-12 International Business Machines Corporation Process for fabricating improved bipolar transistor utilizing selective etching
US4338138A (en) * 1980-03-03 1982-07-06 International Business Machines Corporation Process for fabricating a bipolar transistor
US4318751A (en) * 1980-03-13 1982-03-09 International Business Machines Corporation Self-aligned process for providing an improved high performance bipolar transistor
US4378630A (en) * 1980-05-05 1983-04-05 International Business Machines Corporation Process for fabricating a high performance PNP and NPN structure
US4471522A (en) * 1980-07-08 1984-09-18 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
US4378627A (en) * 1980-07-08 1983-04-05 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
US4394196A (en) * 1980-07-16 1983-07-19 Tokyo Shibaura Denki Kabushiki Kaisha Method of etching, refilling and etching dielectric grooves for isolating micron size device regions
US4419150A (en) * 1980-12-29 1983-12-06 Rockwell International Corporation Method of forming lateral bipolar transistors
JPS57204148A (en) * 1981-06-10 1982-12-14 Toshiba Corp Manufacture of semiconductor device
US4466178A (en) * 1981-06-25 1984-08-21 Rockwell International Corporation Method of making extremely small area PNP lateral transistor by angled implant of deep trenches followed by refilling the same with dielectrics
JPS5848936A (ja) * 1981-09-10 1983-03-23 Fujitsu Ltd 半導体装置の製造方法
US4443932A (en) * 1982-01-18 1984-04-24 Motorla, Inc. Self-aligned oxide isolated process and device
US4495512A (en) * 1982-06-07 1985-01-22 International Business Machines Corporation Self-aligned bipolar transistor with inverted polycide base contact
JPS59119848A (ja) * 1982-12-27 1984-07-11 Fujitsu Ltd 半導体装置の製造方法
US4536950A (en) * 1983-02-10 1985-08-27 Matsushita Electric Industrial Co., Ltd. Method for making semiconductor device
US4572765A (en) * 1983-05-02 1986-02-25 Fairchild Camera & Instrument Corporation Method of fabricating integrated circuit structures using replica patterning
US4752817A (en) * 1983-08-26 1988-06-21 International Business Machines Corporation High performance integrated circuit having modified extrinsic base
EP0166923A3 (en) * 1984-06-29 1987-09-30 International Business Machines Corporation High performance bipolar transistor having a lightly doped guard ring disposed between the emitter and the extrinsic base region
US4583282A (en) * 1984-09-14 1986-04-22 Motorola, Inc. Process for self-aligned buried layer, field guard, and isolation
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation
JPS6181653A (ja) * 1984-09-28 1986-04-25 Nec Corp 半導体装置の自己整合誘電体分離方法
US4571817A (en) * 1985-03-15 1986-02-25 Motorola, Inc. Method of making closely spaced contacts to PN-junction using stacked polysilicon layers, differential etching and ion implantations
US4751554A (en) * 1985-09-27 1988-06-14 Rca Corporation Silicon-on-sapphire integrated circuit and method of making the same
US4758529A (en) * 1985-10-31 1988-07-19 Rca Corporation Method of forming an improved gate dielectric for a MOSFET on an insulating substrate
US4728624A (en) * 1985-10-31 1988-03-01 International Business Machines Corporation Selective epitaxial growth structure and isolation
US4735917A (en) * 1986-04-28 1988-04-05 General Electric Company Silicon-on-sapphire integrated circuits
US4722912A (en) * 1986-04-28 1988-02-02 Rca Corporation Method of forming a semiconductor structure
US4755481A (en) * 1986-05-15 1988-07-05 General Electric Company Method of making a silicon-on-insulator transistor
JPS6318673A (ja) * 1986-07-11 1988-01-26 Yamaha Corp 半導体装置の製法
US4738624A (en) * 1987-04-13 1988-04-19 International Business Machines Corporation Bipolar transistor structure with self-aligned device and isolation and fabrication process therefor
USH763H (en) 1987-09-02 1990-04-03 Bell Telephone Laboratories, Incorporated Submicron bipolar transistor with edge contacts
JPH0256137U (OSRAM) * 1988-10-18 1990-04-24
US5144403A (en) * 1989-02-07 1992-09-01 Hewlett-Packard Company Bipolar transistor with trench-isolated emitter
US5268314A (en) * 1990-01-16 1993-12-07 Philips Electronics North America Corp. Method of forming a self-aligned bipolar transistor
US5159429A (en) * 1990-01-23 1992-10-27 International Business Machines Corporation Semiconductor device structure employing a multi-level epitaxial structure and method of manufacturing same
JP2825169B2 (ja) * 1990-09-17 1998-11-18 キヤノン株式会社 半導体装置
JPH05226352A (ja) * 1992-02-17 1993-09-03 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5736755A (en) * 1992-11-09 1998-04-07 Delco Electronics Corporation Vertical PNP power device with different ballastic resistant vertical PNP transistors
US5266505A (en) * 1992-12-22 1993-11-30 International Business Machines Corporation Image reversal process for self-aligned implants in planar epitaxial-base bipolar transistors
US5444003A (en) * 1993-06-23 1995-08-22 Vlsi Technology, Inc. Method and structure for creating a self-aligned bicmos-compatible bipolar transistor with a laterally graded emitter structure
DE19801095B4 (de) * 1998-01-14 2007-12-13 Infineon Technologies Ag Leistungs-MOSFET
US6121126A (en) * 1998-02-25 2000-09-19 Micron Technologies, Inc. Methods and structures for metal interconnections in integrated circuits
US6143655A (en) 1998-02-25 2000-11-07 Micron Technology, Inc. Methods and structures for silver interconnections in integrated circuits
US6492694B2 (en) 1998-02-27 2002-12-10 Micron Technology, Inc. Highly conductive composite polysilicon gate for CMOS integrated circuits
US6815303B2 (en) * 1998-04-29 2004-11-09 Micron Technology, Inc. Bipolar transistors with low-resistance emitter contacts
DE60040812D1 (de) 1999-03-15 2008-12-24 Matsushita Electric Industrial Co Ltd Herstellungsverfahren für einen Bipolar-Transistor und ein MISFET Halbleiter Bauelement
US6972472B1 (en) 2002-04-02 2005-12-06 Fairchild Semiconductor Corporation Quasi self-aligned single polysilicon bipolar active device with intentional emitter window undercut

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3717507A (en) * 1969-06-19 1973-02-20 Shibaura Electric Co Ltd Method of manufacturing semiconductor devices utilizing ion-implantation and arsenic diffusion
JPS4932028B1 (OSRAM) * 1969-06-24 1974-08-27
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
CA1001771A (en) * 1973-01-15 1976-12-14 Fairchild Camera And Instrument Corporation Method of mos transistor manufacture and resulting structure
JPS5427111B2 (OSRAM) * 1973-05-31 1979-09-07
JPS5624384B2 (OSRAM) * 1974-01-30 1981-06-05
US4115797A (en) * 1976-10-04 1978-09-19 Fairchild Camera And Instrument Corporation Integrated injection logic with heavily doped injector base self-aligned with injector emitter and collector
US4160991A (en) * 1977-10-25 1979-07-10 International Business Machines Corporation High performance bipolar device and method for making same
US4190466A (en) * 1977-12-22 1980-02-26 International Business Machines Corporation Method for making a bipolar transistor structure utilizing self-passivating diffusion sources
JPS54128683A (en) * 1978-03-27 1979-10-05 Ibm Method of fabricating emitterrbase matching bipolar transistor
US4157269A (en) * 1978-06-06 1979-06-05 International Business Machines Corporation Utilizing polysilicon diffusion sources and special masking techniques
US4168999A (en) * 1978-12-26 1979-09-25 Fairchild Camera And Instrument Corporation Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques

Also Published As

Publication number Publication date
JPS56110261A (en) 1981-09-01
JPS6326552B2 (OSRAM) 1988-05-30
US4252582A (en) 1981-02-24
EP0032999A3 (en) 1982-06-30
DE3070658D1 (en) 1985-06-20
EP0032999B1 (de) 1985-05-15
EP0032999A2 (de) 1981-08-05

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