CA1073979A - Integrated programmable logic arrangement - Google Patents

Integrated programmable logic arrangement

Info

Publication number
CA1073979A
CA1073979A CA251,337A CA251337A CA1073979A CA 1073979 A CA1073979 A CA 1073979A CA 251337 A CA251337 A CA 251337A CA 1073979 A CA1073979 A CA 1073979A
Authority
CA
Canada
Prior art keywords
line
matrix
transistors
decoder
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA251,337A
Other languages
English (en)
French (fr)
Inventor
Karlheinrich Horninger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19752519078 external-priority patent/DE2519078C3/de
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of CA1073979A publication Critical patent/CA1073979A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
CA251,337A 1975-04-29 1976-04-28 Integrated programmable logic arrangement Expired CA1073979A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19752519078 DE2519078C3 (de) 1975-04-29 Integrierte programmierbare Logikanordnung

Publications (1)

Publication Number Publication Date
CA1073979A true CA1073979A (en) 1980-03-18

Family

ID=5945320

Family Applications (1)

Application Number Title Priority Date Filing Date
CA251,337A Expired CA1073979A (en) 1975-04-29 1976-04-28 Integrated programmable logic arrangement

Country Status (5)

Country Link
US (1) US4041459A (enExample)
CA (1) CA1073979A (enExample)
FR (1) FR2310040A1 (enExample)
GB (1) GB1552135A (enExample)
IT (1) IT1063025B (enExample)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5911980B2 (ja) * 1975-12-23 1984-03-19 日本電気株式会社 ランダムアクセスメモリソウチ
US4084152A (en) * 1976-06-30 1978-04-11 International Business Machines Corporation Time shared programmable logic array
FR2396468A1 (fr) * 1977-06-30 1979-01-26 Ibm France Perfectionnement aux reseaux logiques programmables
US4177452A (en) * 1978-06-05 1979-12-04 International Business Machines Corporation Electrically programmable logic array
FR2440657A1 (fr) * 1978-10-31 1980-05-30 Ibm France Perfectionnement aux reseaux logiques programmables a fonctions multiples
US4245324A (en) * 1978-12-15 1981-01-13 International Business Machines Corporation Compact programmable logic read array having multiple outputs
DE3044984A1 (de) * 1979-11-30 1982-04-15 Dassault Electronique Integrierte transistorschaltung, insbesondere fuer codierung
US4395646A (en) * 1980-11-03 1983-07-26 International Business Machines Corp. Logic performing cell for use in array structures
FR2493641A1 (fr) * 1980-11-03 1982-05-07 Efcis Reseau logique integre a programmation electrique simplifiee
EP0051693B1 (de) * 1980-11-12 1985-06-19 Ibm Deutschland Gmbh Elektrisch umschaltbarer Festwertspeicher
US4495427A (en) * 1980-12-05 1985-01-22 Rca Corporation Programmable logic gates and networks
US4578771A (en) * 1980-12-29 1986-03-25 International Business Machines Corporation Dynamically reprogrammable array logic system
EP0061512B1 (de) * 1981-04-01 1985-09-18 Deutsche ITT Industries GmbH Integrierte Schaltungsanordnung zum Schreiben, Lesen und Löschen von Speichermatrizen mit Isolierschicht-Feldeffekttransistoren nichtflüchtigen Speicherverhaltens
US4458163A (en) * 1981-07-20 1984-07-03 Texas Instruments Incorporated Programmable architecture logic
DE3135368A1 (de) * 1981-09-07 1983-03-31 Siemens AG, 1000 Berlin und 8000 München Verfahren und anordnung zur funktionspruefung einer programmierbare logikanordnung
JPS5885638A (ja) * 1981-11-17 1983-05-23 Ricoh Co Ltd プログラマブルロジツクアレイ
DE3215671C2 (de) * 1982-04-27 1984-05-03 Siemens AG, 1000 Berlin und 8000 München Programmierbare Logikanordnung
US4488230A (en) * 1982-12-08 1984-12-11 At&T Bell Laboratories Programmed logic array with external signals introduced between its AND plane and its OR plane
JPS59140725A (ja) * 1983-01-31 1984-08-13 Nec Corp 論理回路
US4672240A (en) * 1983-02-07 1987-06-09 Westinghouse Electric Corp. Programmable redundancy circuit
US4554640A (en) * 1984-01-30 1985-11-19 Monolithic Memories, Inc. Programmable array logic circuit with shared product terms
GB2171231B (en) * 1985-02-14 1989-11-01 Intel Corp Software programmable logic array
JPH073838B2 (ja) * 1985-02-28 1995-01-18 株式会社東芝 半導体集積回路
JP2540794B2 (ja) * 1985-03-04 1996-10-09 株式会社日立製作所 プログラマブルロジツクアレイ回路
US4761768A (en) * 1985-03-04 1988-08-02 Lattice Semiconductor Corporation Programmable logic device
US4766569A (en) * 1985-03-04 1988-08-23 Lattice Semiconductor Corporation Programmable logic array
US4879688A (en) * 1985-03-04 1989-11-07 Lattice Semiconductor Corporation In-system programmable logic device
US4641046A (en) * 1985-06-17 1987-02-03 Signetics Corporation NOR gate with logical low output clamp
US4791603A (en) * 1986-07-18 1988-12-13 Honeywell Inc. Dynamically reconfigurable array logic
JPS63310215A (ja) * 1987-06-12 1988-12-19 Fujitsu Ltd プログラマブル論理回路
JPS6478023A (en) * 1987-09-18 1989-03-23 Fujitsu Ltd Programmable logic device
US5655113A (en) * 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3940740A (en) * 1973-06-27 1976-02-24 Actron Industries, Inc. Method for providing reconfigurable microelectronic circuit devices and products produced thereby
DE2347968C3 (de) * 1973-09-24 1980-06-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Assoziative Speicherzelle
US3895360A (en) * 1974-01-29 1975-07-15 Westinghouse Electric Corp Block oriented random access memory
US3924243A (en) * 1974-08-06 1975-12-02 Ibm Cross-field-partitioning in array logic modules

Also Published As

Publication number Publication date
IT1063025B (it) 1985-02-11
FR2310040A1 (fr) 1976-11-26
US4041459A (en) 1977-08-09
FR2310040B1 (enExample) 1978-05-19
DE2519078A1 (de) 1976-11-04
DE2519078B2 (de) 1977-03-03
GB1552135A (en) 1979-09-12

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