CA1058330A - Process for depositing conductive layers on substrates - Google Patents

Process for depositing conductive layers on substrates

Info

Publication number
CA1058330A
CA1058330A CA259,725A CA259725A CA1058330A CA 1058330 A CA1058330 A CA 1058330A CA 259725 A CA259725 A CA 259725A CA 1058330 A CA1058330 A CA 1058330A
Authority
CA
Canada
Prior art keywords
layer
metal
adhesion
thickness
gold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA259,725A
Other languages
English (en)
French (fr)
Inventor
Donald M. Mattox
Paul H. Holloway
Gerald C. Nelson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Department of Energy
Original Assignee
US Department of Energy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by US Department of Energy filed Critical US Department of Energy
Application granted granted Critical
Publication of CA1058330A publication Critical patent/CA1058330A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Physical Vapour Deposition (AREA)
  • Manufacturing Of Printed Wiring (AREA)
CA259,725A 1975-10-30 1976-08-24 Process for depositing conductive layers on substrates Expired CA1058330A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US62742075A 1975-10-30 1975-10-30

Publications (1)

Publication Number Publication Date
CA1058330A true CA1058330A (en) 1979-07-10

Family

ID=24514575

Family Applications (1)

Application Number Title Priority Date Filing Date
CA259,725A Expired CA1058330A (en) 1975-10-30 1976-08-24 Process for depositing conductive layers on substrates

Country Status (5)

Country Link
JP (1) JPS5257972A (show.php)
CA (1) CA1058330A (show.php)
DE (1) DE2649091A1 (show.php)
FR (1) FR2330245A1 (show.php)
GB (1) GB1539272A (show.php)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0074605B1 (en) * 1981-09-11 1990-08-29 Kabushiki Kaisha Toshiba Method for manufacturing multilayer circuit substrate
JPS59167096A (ja) * 1983-03-11 1984-09-20 日本電気株式会社 回路基板
JPH0732158B2 (ja) * 1988-04-08 1995-04-10 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 電子部品のための多層金属構造

Also Published As

Publication number Publication date
FR2330245A1 (fr) 1977-05-27
FR2330245B3 (show.php) 1979-07-13
DE2649091A1 (de) 1977-05-12
JPS5257972A (en) 1977-05-12
GB1539272A (en) 1979-01-31

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