CA1058330A - Process for depositing conductive layers on substrates - Google Patents
Process for depositing conductive layers on substratesInfo
- Publication number
- CA1058330A CA1058330A CA259,725A CA259725A CA1058330A CA 1058330 A CA1058330 A CA 1058330A CA 259725 A CA259725 A CA 259725A CA 1058330 A CA1058330 A CA 1058330A
- Authority
- CA
- Canada
- Prior art keywords
- layer
- metal
- adhesion
- thickness
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Physical Vapour Deposition (AREA)
- Manufacturing Of Printed Wiring (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US62742075A | 1975-10-30 | 1975-10-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1058330A true CA1058330A (en) | 1979-07-10 |
Family
ID=24514575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA259,725A Expired CA1058330A (en) | 1975-10-30 | 1976-08-24 | Process for depositing conductive layers on substrates |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5257972A (OSRAM) |
| CA (1) | CA1058330A (OSRAM) |
| DE (1) | DE2649091A1 (OSRAM) |
| FR (1) | FR2330245A1 (OSRAM) |
| GB (1) | GB1539272A (OSRAM) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0074605B1 (en) * | 1981-09-11 | 1990-08-29 | Kabushiki Kaisha Toshiba | Method for manufacturing multilayer circuit substrate |
| JPS59167096A (ja) * | 1983-03-11 | 1984-09-20 | 日本電気株式会社 | 回路基板 |
| JPH0732158B2 (ja) * | 1988-04-08 | 1995-04-10 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | 電子部品のための多層金属構造 |
-
1976
- 1976-08-23 GB GB34967/76A patent/GB1539272A/en not_active Expired
- 1976-08-24 CA CA259,725A patent/CA1058330A/en not_active Expired
- 1976-10-28 DE DE19762649091 patent/DE2649091A1/de active Pending
- 1976-10-29 JP JP51131173A patent/JPS5257972A/ja active Pending
- 1976-10-29 FR FR7632825A patent/FR2330245A1/fr active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| FR2330245A1 (fr) | 1977-05-27 |
| FR2330245B3 (OSRAM) | 1979-07-13 |
| DE2649091A1 (de) | 1977-05-12 |
| JPS5257972A (en) | 1977-05-12 |
| GB1539272A (en) | 1979-01-31 |
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