BRPI0404015A - Esvaziamento lento de armazenamentos temporários de pesquisa paralela de tradução - Google Patents

Esvaziamento lento de armazenamentos temporários de pesquisa paralela de tradução

Info

Publication number
BRPI0404015A
BRPI0404015A BR0404015-5A BRPI0404015A BRPI0404015A BR PI0404015 A BRPI0404015 A BR PI0404015A BR PI0404015 A BRPI0404015 A BR PI0404015A BR PI0404015 A BRPI0404015 A BR PI0404015A
Authority
BR
Brazil
Prior art keywords
processor
tlb
counter
page
mappings
Prior art date
Application number
BR0404015-5A
Other languages
English (en)
Inventor
Ernest S Cohen
Original Assignee
Microsoft Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Corp filed Critical Microsoft Corp
Publication of BRPI0404015A publication Critical patent/BRPI0404015A/pt
Publication of BRPI0404015B1 publication Critical patent/BRPI0404015B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/682—Multiprocessor TLB consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)

Abstract

"ESVAZIAMENTO LENTO DE ARMAZENAMENTOS TEMPORáRIOS DE PESQUISA PARALELA DE TRADUçãO". Trata-se de um controle de tradução de endereço (ATC) que limita os mapeamentos entre endereços virtual e físico de modo a implementar uma política de acesso à memória. Cada processador em um sistema com múltiplos processadores mantém uma memória intermediária de tradução de exame à distância (TLB) que coloca no cache mapeamentos para acelerar a tradução dos endereços virtuais. Cada processador também mantém um contador. Cada vez que a TLB de um processador é esvaziada, o contador do processador é incrementado. Quando uma ligação para uma página é removida de um mapa de tradução de endereço, os valores de contador para todos os processadores são gravados. Quando esta página é acessada por um processador, os valores de contador gravados são comparados com o valor corrente do contador do processador para determinar se a TLB do processador foi esvaziada desde que a ligação com a página foi removida a partir do mapa. Uma operação de esvaziamento de TLB onerosa é retardada até necessário, mas ainda ocorre cedo o suficiente para impedir uma entrada da TLB invalidada de ser utilizada para violar a política de acesso.
BRPI0404015A 2003-11-26 2004-09-16 esvaziamento lento de armazenamentos temporários de pesquisa paralela de tradução BRPI0404015B1 (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/723,823 US7069389B2 (en) 2003-11-26 2003-11-26 Lazy flushing of translation lookaside buffers

Publications (2)

Publication Number Publication Date
BRPI0404015A true BRPI0404015A (pt) 2005-07-12
BRPI0404015B1 BRPI0404015B1 (pt) 2017-01-31

Family

ID=34465717

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0404015A BRPI0404015B1 (pt) 2003-11-26 2004-09-16 esvaziamento lento de armazenamentos temporários de pesquisa paralela de tradução

Country Status (12)

Country Link
US (2) US7069389B2 (pt)
EP (1) EP1536341B1 (pt)
JP (1) JP3944504B2 (pt)
KR (1) KR100918530B1 (pt)
CN (1) CN100424657C (pt)
AT (1) ATE457495T1 (pt)
AU (1) AU2004218704B2 (pt)
BR (1) BRPI0404015B1 (pt)
CA (1) CA2483938C (pt)
DE (1) DE602004025442D1 (pt)
MX (1) MXPA04011270A (pt)
RU (1) RU2361267C2 (pt)

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Also Published As

Publication number Publication date
US20060161734A1 (en) 2006-07-20
CN1622060A (zh) 2005-06-01
CN100424657C (zh) 2008-10-08
ATE457495T1 (de) 2010-02-15
CA2483938C (en) 2015-05-12
JP3944504B2 (ja) 2007-07-11
CA2483938A1 (en) 2005-05-26
KR20050051540A (ko) 2005-06-01
DE602004025442D1 (de) 2010-03-25
JP2005158040A (ja) 2005-06-16
KR100918530B1 (ko) 2009-09-21
MXPA04011270A (es) 2005-05-30
AU2004218704A1 (en) 2005-06-09
US7069389B2 (en) 2006-06-27
EP1536341A2 (en) 2005-06-01
RU2004134452A (ru) 2006-05-10
RU2361267C2 (ru) 2009-07-10
EP1536341B1 (en) 2010-02-10
EP1536341A3 (en) 2006-10-25
AU2004218704B2 (en) 2010-02-18
US7287124B2 (en) 2007-10-23
BRPI0404015B1 (pt) 2017-01-31
US20050114607A1 (en) 2005-05-26

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Owner name: MICROSOFT TECHNOLOGY LICENSING, LLC (US)

B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]
B21F Lapse acc. art. 78, item iv - on non-payment of the annual fees in time

Free format text: REFERENTE A 15A ANUIDADE.

B24J Lapse because of non-payment of annual fees (definitively: art 78 iv lpi, resolution 113/2013 art. 12)

Free format text: EM VIRTUDE DA EXTINCAO PUBLICADA NA RPI 2531 DE 09-07-2019 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDA A EXTINCAO DA PATENTE E SEUS CERTIFICADOS, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.