BR9900110A - Aparelho para divisão de frequência de módulo duplo de contador único. - Google Patents

Aparelho para divisão de frequência de módulo duplo de contador único.

Info

Publication number
BR9900110A
BR9900110A BR9900110-1A BR9900110A BR9900110A BR 9900110 A BR9900110 A BR 9900110A BR 9900110 A BR9900110 A BR 9900110A BR 9900110 A BR9900110 A BR 9900110A
Authority
BR
Brazil
Prior art keywords
programmable
output
divider
signal
frequency division
Prior art date
Application number
BR9900110-1A
Other languages
English (en)
Inventor
Carl Lynn Shurboff
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of BR9900110A publication Critical patent/BR9900110A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Measuring Frequencies, Analyzing Spectra (AREA)
  • Transceivers (AREA)

Abstract

<B>"APARELHO PARA DIVISãO DE FREQUêNCIA DE MóDULO DUPLO DE CONTADOR úNICO"<D>. Um aparelho para divisão de frequência de módulo dual de contador único (400) utiliza um divisor programável (508) configurado para receber um sinal de entrada de RF na entrada (500) do sistema divisor e um controle de módulo (516) produziro por um contador programável (510). O controle de módulo (516) ajusta um valor de divisão do divisor programável (508) para produzir um sinal dividido em uma saída (514) do divisor programável. Um comutador (512) é configurado para receber uma primeira instrução de proramação na primeira entrada (504) de intrução de programação e uma segunda instrução de programação em uma segunda entrada (506) de instrução de programação pra produzir um controle de contagem (518). O contador programável (510) recebe o sinal dividido que aparece na saída (514) do divisor programável e do controle de contagem (518). O controle de contagem (518) ajusta o valor de contagem do contador programável (510). O contador programável (510) conta períodos do sinal dividido que aparece na saída (514) do divisor programável para produzir o sinal de saída dividido na saída (502) do sistema divisor.
BR9900110-1A 1998-01-20 1999-01-19 Aparelho para divisão de frequência de módulo duplo de contador único. BR9900110A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/009,477 US6035182A (en) 1998-01-20 1998-01-20 Single counter dual modulus frequency division apparatus

Publications (1)

Publication Number Publication Date
BR9900110A true BR9900110A (pt) 2000-01-04

Family

ID=21737893

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9900110-1A BR9900110A (pt) 1998-01-20 1999-01-19 Aparelho para divisão de frequência de módulo duplo de contador único.

Country Status (6)

Country Link
US (1) US6035182A (pt)
JP (1) JPH11317661A (pt)
BR (1) BR9900110A (pt)
FR (1) FR2775398A1 (pt)
GB (1) GB2333622A (pt)
MX (1) MXPA99000767A (pt)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19930168C2 (de) * 1999-06-30 2001-07-19 Infineon Technologies Ag Schaltungsanordnung für einen Frequenzteiler
US6566966B1 (en) * 2000-09-18 2003-05-20 Texas Instruments Incorporated Fast lock/self-tuning VCO based PLL
US6760571B2 (en) * 2001-12-18 2004-07-06 The United States Of America As Represented By The Secretary Of The Navy Automatic frequency deviation detection and correction apparatus
US6725245B2 (en) * 2002-05-03 2004-04-20 P.C. Peripherals, Inc High speed programmable counter architecture
FR2851094B1 (fr) * 2003-02-07 2005-04-15 Thales Sa Diviseur de frequence a structure entonnoir
FR2865326B1 (fr) * 2004-01-20 2006-07-21 Thales Sa Procede et dispositif de division de frequence
KR100550875B1 (ko) * 2004-02-27 2006-02-10 삼성전기주식회사 협대역 밴드패스 필터를 포함하는 고주파 모듈레이터
CN100594679C (zh) * 2007-05-24 2010-03-17 中国科学院微电子研究所 一种双模分频器
CN100568735C (zh) * 2007-09-24 2009-12-09 威盛电子股份有限公司 分频器
KR101595287B1 (ko) * 2009-03-09 2016-02-18 삼성전자주식회사 클럭 분주 회로
US9543960B1 (en) * 2015-07-28 2017-01-10 Integrated Device Technology, Inc. Multi-stage frequency dividers having duty cycle correction circuits therein
DE112019006377T5 (de) * 2018-12-20 2021-09-02 Viavi Solutions Inc. System und verfahren zur signalumabtastung

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4024476A (en) * 1976-02-02 1977-05-17 Rca Corporation Programmable frequency divider for a television receiver frequency synthesizer
US4053739A (en) * 1976-08-11 1977-10-11 Motorola, Inc. Dual modulus programmable counter
US4084082A (en) * 1976-10-12 1978-04-11 Fairchild Camera And Instrument Corporation Programmable counter
US4325031A (en) * 1980-02-13 1982-04-13 Motorola, Inc. Divider with dual modulus prescaler for phase locked loop frequency synthesizer
JPS5718129A (en) * 1980-07-07 1982-01-29 Nec Corp Pulse swallow frequency divider
US4856032A (en) * 1987-01-12 1989-08-08 Motorola, Inc. High speed programmable frequency divider and PLL
US4891825A (en) * 1988-02-09 1990-01-02 Motorola, Inc. Fully synchronized programmable counter with a near 50% duty cycle output signal
US5180993A (en) * 1990-01-15 1993-01-19 Telefonaktiebolaget L M Ericsson Method and arrangement for frequency synthesis
US5065408A (en) * 1990-04-26 1991-11-12 Motorola, Inc. Fractional-division synthesizer for a voice/data communications systems
US5066927A (en) * 1990-09-06 1991-11-19 Ericsson Ge Mobile Communication Holding, Inc. Dual modulus counter for use in a phase locked loop
US5150082A (en) * 1992-02-21 1992-09-22 Hewlett-Packard Company Center frequency calibration for DC coupled frequency modulation in a phase-locked loop
US5351015A (en) * 1993-02-03 1994-09-27 Silicon Systems, Inc. Time based data separator zone change sequence
US5535432A (en) * 1994-09-14 1996-07-09 Ericsson Ge Mobile Communications Inc. Dual-mode satellite/cellular phone with a frequency synthesizer
US5825213A (en) * 1996-12-16 1998-10-20 Motorola, Inc. Method and apparatus for frequency synthesis

Also Published As

Publication number Publication date
GB2333622A (en) 1999-07-28
FR2775398A1 (fr) 1999-08-27
US6035182A (en) 2000-03-07
JPH11317661A (ja) 1999-11-16
MXPA99000767A (es) 2005-04-28

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Legal Events

Date Code Title Description
B07A Technical examination (opinion): publication of technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]

Free format text: INDEFIRO O PEDIDO DE ACORDO COM O ART. 8O COMBINADO COM O ART. 13 DA LPI

B09B Patent application refused [chapter 9.2 patent gazette]

Free format text: MANTIDO O INDEFERIMENTO UMA VEZ QUE NAO FOI APRESENTADO RECURSO DENTRO DO PRAZO LEGAL.