MX153125A - Mejoras a controlador de entrada/salida con multiples modos operativos - Google Patents

Mejoras a controlador de entrada/salida con multiples modos operativos

Info

Publication number
MX153125A
MX153125A MX196107A MX19610783A MX153125A MX 153125 A MX153125 A MX 153125A MX 196107 A MX196107 A MX 196107A MX 19610783 A MX19610783 A MX 19610783A MX 153125 A MX153125 A MX 153125A
Authority
MX
Mexico
Prior art keywords
input
operating modes
output controller
multiple operating
controller
Prior art date
Application number
MX196107A
Other languages
English (en)
Inventor
Chester A Heath
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of MX153125A publication Critical patent/MX153125A/es

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bus Control (AREA)
  • Document Processing Apparatus (AREA)
MX196107A 1982-02-02 1983-02-01 Mejoras a controlador de entrada/salida con multiples modos operativos MX153125A (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/345,177 US4509113A (en) 1982-02-02 1982-02-02 Peripheral interface adapter circuit for use in I/O controller card having multiple modes of operation

Publications (1)

Publication Number Publication Date
MX153125A true MX153125A (es) 1986-08-06

Family

ID=23353885

Family Applications (1)

Application Number Title Priority Date Filing Date
MX196107A MX153125A (es) 1982-02-02 1983-02-01 Mejoras a controlador de entrada/salida con multiples modos operativos

Country Status (6)

Country Link
US (1) US4509113A (es)
JP (1) JPS58134324A (es)
AU (1) AU554821B2 (es)
BR (1) BR8300365A (es)
CA (1) CA1184311A (es)
MX (1) MX153125A (es)

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JPH0731586B2 (ja) * 1991-07-23 1995-04-10 インターナショナル・ビジネス・マシーンズ・コーポレイション ディスプレイ・アダプタ・インターフェース装置及び方法
JP2599539B2 (ja) * 1991-10-15 1997-04-09 インターナショナル・ビジネス・マシーンズ・コーポレイション 直接メモリ・アクセス装置及びルック・アヘッド装置
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CA2098461A1 (en) * 1992-06-17 1993-12-18 Antony S. Williams Method and system for registering data formats for objects
EP0582535A1 (en) * 1992-07-07 1994-02-09 International Business Machines Corporation Communication system and method utilizing picoprocessors for performing complex functions out of main communication data path
TW390446U (en) * 1992-10-01 2000-05-11 Hudson Soft Co Ltd Information processing system
JPH06100998B2 (ja) * 1992-10-02 1994-12-12 インターナショナル・ビジネス・マシーンズ・コーポレイション データ転送制御用インターフェース回路
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US5537607A (en) * 1993-04-28 1996-07-16 International Business Machines Corporation Field programmable general purpose interface adapter for connecting peripheral devices within a computer system
JP3264465B2 (ja) * 1993-06-30 2002-03-11 株式会社日立製作所 記憶システム
US6289402B1 (en) * 1993-07-23 2001-09-11 Amiga Development Llc Bidirectional data transfer protocol primarily controlled by a peripheral device
JP3478565B2 (ja) * 1993-08-06 2003-12-15 ブラザー工業株式会社 パラレルインタフェース回路
EP0660239A1 (en) * 1993-12-17 1995-06-28 International Business Machines Corporation Data transfer between computing elements
US5701514A (en) * 1994-04-01 1997-12-23 International Business Machines Corporation System providing user definable selection of different data transmission modes of drivers of an I/O controller transmitting to peripherals with different data transmission rate
US5432698A (en) * 1994-05-31 1995-07-11 Modular Instruments, Inc. Data input and output controller for anesthesia monitoring system
US5701515A (en) * 1994-06-16 1997-12-23 Apple Computer, Inc. Interface for switching plurality of pin contacts to transmit data line and plurality of pin contacts to receive data line to interface with serial controller
US5794014A (en) * 1994-06-27 1998-08-11 Cirrus Logic, Inc. Method and apparatus for interfacing between peripherals of multiple formats and a single system bus
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Also Published As

Publication number Publication date
JPS629948B2 (es) 1987-03-03
JPS58134324A (ja) 1983-08-10
US4509113A (en) 1985-04-02
AU554821B2 (en) 1986-09-04
BR8300365A (pt) 1983-10-25
CA1184311A (en) 1985-03-19
AU1073583A (en) 1983-08-11

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