BR9507454A - Unidade aperfeiçoada de memória de sistema de custo/desempenho que utiliza uma memória de acesso aleatório com uma saída de dados ampliada - Google Patents

Unidade aperfeiçoada de memória de sistema de custo/desempenho que utiliza uma memória de acesso aleatório com uma saída de dados ampliada

Info

Publication number
BR9507454A
BR9507454A BR9507454A BR9507454A BR9507454A BR 9507454 A BR9507454 A BR 9507454A BR 9507454 A BR9507454 A BR 9507454A BR 9507454 A BR9507454 A BR 9507454A BR 9507454 A BR9507454 A BR 9507454A
Authority
BR
Brazil
Prior art keywords
random access
data output
extended data
performance system
access memory
Prior art date
Application number
BR9507454A
Other languages
English (en)
Inventor
Aniruddha Kundu
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR9507454A publication Critical patent/BR9507454A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G11C7/1024—Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Microcomputers (AREA)
BR9507454A 1994-04-11 1995-04-03 Unidade aperfeiçoada de memória de sistema de custo/desempenho que utiliza uma memória de acesso aleatório com uma saída de dados ampliada BR9507454A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/225,522 US5692148A (en) 1994-04-11 1994-04-11 Method and apparatus for improving system memory cost/performance using extended data out (EDO)DRAM and split column addresses

Publications (1)

Publication Number Publication Date
BR9507454A true BR9507454A (pt) 1999-06-15

Family

ID=22845217

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9507454A BR9507454A (pt) 1994-04-11 1995-04-03 Unidade aperfeiçoada de memória de sistema de custo/desempenho que utiliza uma memória de acesso aleatório com uma saída de dados ampliada

Country Status (6)

Country Link
US (1) US5692148A (pt)
EP (1) EP0755539A4 (pt)
AU (1) AU2206895A (pt)
BR (1) BR9507454A (pt)
CA (1) CA2186139C (pt)
WO (1) WO1995028669A2 (pt)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020147884A1 (en) * 2001-04-05 2002-10-10 Michael Peters Method and circuit for increasing the memory access speed of an enhanced synchronous SDRAM
US6813679B2 (en) * 2002-06-20 2004-11-02 Purple Mountain Server Llc Method and circuit for increasing the memory access speed of an enhanced synchronous SDRAM
US10936480B2 (en) * 2019-05-31 2021-03-02 Microsoft Technology Licensing, Llc Memory management for multiple process instances

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117492A (ja) * 1983-11-29 1985-06-24 Fujitsu Ltd 半導体記憶装置
JPS637591A (ja) * 1986-06-25 1988-01-13 Nec Corp アドレスマルチプレクス型半導体メモリ
DE3780551T2 (de) * 1986-09-04 1993-03-11 Fujitsu Ltd Speichereinrichtung unter verwendung von adressenmultiplex.
US4792929A (en) * 1987-03-23 1988-12-20 Zenith Electronics Corporation Data processing system with extended memory access
AU611275B2 (en) * 1988-05-26 1991-06-06 International Business Machines Corporation Apparatus and method for accessing data stored in a page mode memory
US4953130A (en) * 1988-06-27 1990-08-28 Texas Instruments, Incorporated Memory circuit with extended valid data output time
JP2555900B2 (ja) * 1990-02-06 1996-11-20 日本電気株式会社 半導体メモリの出力制御回路
JPH07192470A (ja) * 1993-03-08 1995-07-28 Nec Ic Microcomput Syst Ltd 半導体メモリの出力回路
US5349566A (en) * 1993-05-19 1994-09-20 Micron Semiconductor, Inc. Memory device with pulse circuit for timing data output, and method for outputting data

Also Published As

Publication number Publication date
CA2186139A1 (en) 1995-10-26
AU2206895A (en) 1995-11-10
MX9604528A (es) 1997-09-30
WO1995028669A2 (en) 1995-10-26
EP0755539A4 (en) 1997-11-12
EP0755539A1 (en) 1997-01-29
US5692148A (en) 1997-11-25
CA2186139C (en) 2004-11-16
WO1995028669A3 (en) 1995-11-30

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Legal Events

Date Code Title Description
EG Technical examination (opinion): publication of technical examination (opinion)
FB36 Technical and formal requirements: requirement - article 36 of industrial property law
FF Decision: intention to grant
FG9A Patent or certificate of addition granted
B24H Lapse because of non-payment of annual fees (definitively: art 78 iv lpi)
B24F Patent annual fee: publication cancelled

Free format text: ANULADA A PUBLICACAO CODIGO 24.8 NA RPI NO 2258 DE 15/04/2014 POR TER SIDO INDEVIDA.

B21F Lapse acc. art. 78, item iv - on non-payment of the annual fees in time

Free format text: REFERENTE AS 17A, 18A, 19A E 20A ANUIDADES.

B24J Lapse because of non-payment of annual fees (definitively: art 78 iv lpi, resolution 113/2013 art. 12)

Free format text: EM VIRTUDE DA EXTINCAO PUBLICADA NA RPI 2607 DE 22-12-2020 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDA A EXTINCAO DA PATENTE E SEUS CERTIFICADOS, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.