BR112022018903A2 - Aparelho de pacote híbrido e método de fabricação - Google Patents

Aparelho de pacote híbrido e método de fabricação

Info

Publication number
BR112022018903A2
BR112022018903A2 BR112022018903A BR112022018903A BR112022018903A2 BR 112022018903 A2 BR112022018903 A2 BR 112022018903A2 BR 112022018903 A BR112022018903 A BR 112022018903A BR 112022018903 A BR112022018903 A BR 112022018903A BR 112022018903 A2 BR112022018903 A2 BR 112022018903A2
Authority
BR
Brazil
Prior art keywords
substrate
manufacturing
hybrid package
metallization structure
appliance
Prior art date
Application number
BR112022018903A
Other languages
English (en)
Inventor
Patil Aniket
Bok We Hong
Navaja Brigham
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112022018903A2 publication Critical patent/BR112022018903A2/pt

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

APARELHO DE PACOTE HÍBRIDO E MÉTODO DE FABRICAÇÃO. A presente invenção se refere a algumas características que pertencem a um pacote híbrido que inclui uma pastilha, uma primeira estrutura de substrato e uma primeira estrutura de metalização que é pelo menos parcialmente coplanar ao substrato. A pastilha é eletricamente acoplada à primeira estrutura de metalização e ao primeiro substrato através de uma segunda estrutura de metalização. A primeira estrutura de metalização é configurada para fornecer um caminho elétrico para sinalização de dados. A segunda estrutura de metalização é configurada como um plano de terra e é acoplada a um sinal terra. A primeira estrutura de substrato é configurada para fornecer um caminho elétrico para sinalização de energia.
BR112022018903A 2020-03-31 2021-03-30 Aparelho de pacote híbrido e método de fabricação BR112022018903A2 (pt)

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US202063002750P 2020-03-31 2020-03-31
US17/211,164 US11948877B2 (en) 2020-03-31 2021-03-24 Hybrid package apparatus and method of fabricating
PCT/US2021/024783 WO2021202454A1 (en) 2020-03-31 2021-03-30 Hybrid package apparatus and method of fabricating

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US20230307336A1 (en) * 2022-03-25 2023-09-28 Qualcomm Incorporated Package substrates employing pad metallization layer for increased signal routing capacity, and related integrated circuit (ic) packages and fabrication methods

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US6281446B1 (en) * 1998-02-16 2001-08-28 Matsushita Electric Industrial Co., Ltd. Multi-layered circuit board and method of manufacturing the same
US20080239685A1 (en) 2007-03-27 2008-10-02 Tadahiko Kawabe Capacitor built-in wiring board
TWI492680B (zh) * 2011-08-05 2015-07-11 Unimicron Technology Corp 嵌埋有中介層之封裝基板及其製法
US8975726B2 (en) * 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US10453785B2 (en) 2014-08-07 2019-10-22 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming double-sided fan-out wafer level package
CN108780785A (zh) * 2016-03-30 2018-11-09 英特尔公司 混合微电子基底
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KR102504293B1 (ko) 2017-11-29 2023-02-27 삼성전자 주식회사 패키지 온 패키지 형태의 반도체 패키지
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TWI670824B (zh) * 2018-03-09 2019-09-01 欣興電子股份有限公司 封裝結構
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US20210305141A1 (en) 2021-09-30
CN115335989A (zh) 2022-11-11
TW202145391A (zh) 2021-12-01
EP4128340A1 (en) 2023-02-08
US11948877B2 (en) 2024-04-02
WO2021202454A1 (en) 2021-10-07

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