BR112017025625A2 - reordenação de transação e tradução com multi-thread para unidades de gerenciamento de memória - Google Patents

reordenação de transação e tradução com multi-thread para unidades de gerenciamento de memória

Info

Publication number
BR112017025625A2
BR112017025625A2 BR112017025625A BR112017025625A BR112017025625A2 BR 112017025625 A2 BR112017025625 A2 BR 112017025625A2 BR 112017025625 A BR112017025625 A BR 112017025625A BR 112017025625 A BR112017025625 A BR 112017025625A BR 112017025625 A2 BR112017025625 A2 BR 112017025625A2
Authority
BR
Brazil
Prior art keywords
translation
address
threaded
memory management
management units
Prior art date
Application number
BR112017025625A
Other languages
English (en)
Portuguese (pt)
Inventor
Miretski Alexander
Javier Moreira Carlos
Edward Podaima Jason
John Ernewein Kyle
Somasundaram Manokanthan
Varia Meghal
Umar Choudry Muhammad
Christopher John Wiercienski Paul
Monier Gadelrab Serag
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112017025625A2 publication Critical patent/BR112017025625A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/655—Same page detection
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/682—Multiprocessor TLB consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/683—Invalidation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/684—TLB miss handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
BR112017025625A 2015-05-29 2016-04-27 reordenação de transação e tradução com multi-thread para unidades de gerenciamento de memória BR112017025625A2 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201562168712P 2015-05-29 2015-05-29
US14/859,351 US10007619B2 (en) 2015-05-29 2015-09-20 Multi-threaded translation and transaction re-ordering for memory management units
PCT/US2016/029502 WO2016195850A1 (en) 2015-05-29 2016-04-27 Multi-threaded translation and transaction re-ordering for memory management units

Publications (1)

Publication Number Publication Date
BR112017025625A2 true BR112017025625A2 (pt) 2018-08-07

Family

ID=57397568

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112017025625A BR112017025625A2 (pt) 2015-05-29 2016-04-27 reordenação de transação e tradução com multi-thread para unidades de gerenciamento de memória

Country Status (9)

Country Link
US (1) US10007619B2 (enExample)
EP (1) EP3304320A1 (enExample)
JP (1) JP2018519581A (enExample)
KR (1) KR20180013924A (enExample)
CN (1) CN107710173A (enExample)
BR (1) BR112017025625A2 (enExample)
CA (1) CA2983797A1 (enExample)
TW (1) TW201710908A (enExample)
WO (1) WO2016195850A1 (enExample)

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US9830224B2 (en) * 2013-03-15 2017-11-28 Nvidia Corporation Selective fault stalling for a GPU memory pipeline in a unified virtual memory system
US10509729B2 (en) 2016-01-13 2019-12-17 Intel Corporation Address translation for scalable virtualization of input/output devices
US10228981B2 (en) * 2017-05-02 2019-03-12 Intel Corporation High-performance input-output devices supporting scalable virtualization
US10635654B2 (en) * 2017-06-12 2020-04-28 Samsung Electronics Co., Ltd. Data journaling for large solid state storage devices with low DRAM/SRAM
US10649912B2 (en) * 2017-07-14 2020-05-12 International Business Machines Corporation Method and apparatus for an efficient TLB lookup
US20190087351A1 (en) * 2017-09-20 2019-03-21 Qualcomm Incorporated Transaction dispatcher for memory management unit
US10628072B2 (en) 2018-08-21 2020-04-21 Samsung Electronics Co., Ltd. Scalable architecture enabling large memory system for in-memory computations
GB2578099B (en) * 2018-10-15 2021-05-12 Advanced Risc Mach Ltd Memory access control
CN113127064B (zh) * 2019-12-31 2025-02-14 深圳云天励飞技术有限公司 一种并发调度和执行时序数据的方法及相关装置
KR102824954B1 (ko) * 2020-07-24 2025-06-25 한국전자통신연구원 병렬 처리 시스템에서의 메모리 액세스 제어 장치 및 메모리 액세스 제어 방법
US11636043B2 (en) 2021-08-30 2023-04-25 International Business Machines Corporation Sleeping and waking-up address translation that conflicts with translation level of active page table walks

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US8271700B1 (en) * 2007-11-23 2012-09-18 Pmc-Sierra Us, Inc. Logical address direct memory access with multiple concurrent physical ports and internal switching
US8108584B2 (en) * 2008-10-15 2012-01-31 Intel Corporation Use of completer knowledge of memory region ordering requirements to modify transaction attributes
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Also Published As

Publication number Publication date
JP2018519581A (ja) 2018-07-19
CN107710173A (zh) 2018-02-16
CA2983797A1 (en) 2016-12-08
US10007619B2 (en) 2018-06-26
KR20180013924A (ko) 2018-02-07
TW201710908A (zh) 2017-03-16
WO2016195850A1 (en) 2016-12-08
EP3304320A1 (en) 2018-04-11
US20160350234A1 (en) 2016-12-01

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Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal acc. article 33 of ipl - extension of time limit for request of examination expired