JP2018519581A - メモリ管理ユニットに対するマルチスレッド変換およびトランザクション並べ替え - Google Patents

メモリ管理ユニットに対するマルチスレッド変換およびトランザクション並べ替え Download PDF

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JP2018519581A
JP2018519581A JP2017560966A JP2017560966A JP2018519581A JP 2018519581 A JP2018519581 A JP 2018519581A JP 2017560966 A JP2017560966 A JP 2017560966A JP 2017560966 A JP2017560966 A JP 2017560966A JP 2018519581 A JP2018519581 A JP 2018519581A
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translation
address translation
requests
address
cache
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JP2018519581A5 (enExample
Inventor
ジェイソン・エドワード・ポダイマ
ポール・クリストファー・ジョン・ウィアーシエンスキー
カルロス・ハビエル・モレイラ
アレクサンダー・マイアトスキー
メガール・ヴァリア
カイル・ジョン・アーンウェイン
マノカンタン・ソマスンダラム
ムハンマド・ウマー・チャウドリー
セラッグ・モニア・ガデルラブ
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/655—Same page detection
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/682—Multiprocessor TLB consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/683—Invalidation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/684—TLB miss handling

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2017560966A 2015-05-29 2016-04-27 メモリ管理ユニットに対するマルチスレッド変換およびトランザクション並べ替え Ceased JP2018519581A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562168712P 2015-05-29 2015-05-29
US62/168,712 2015-05-29
US14/859,351 2015-09-20
US14/859,351 US10007619B2 (en) 2015-05-29 2015-09-20 Multi-threaded translation and transaction re-ordering for memory management units
PCT/US2016/029502 WO2016195850A1 (en) 2015-05-29 2016-04-27 Multi-threaded translation and transaction re-ordering for memory management units

Publications (2)

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JP2018519581A true JP2018519581A (ja) 2018-07-19
JP2018519581A5 JP2018519581A5 (enExample) 2018-09-06

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Country Link
US (1) US10007619B2 (enExample)
EP (1) EP3304320A1 (enExample)
JP (1) JP2018519581A (enExample)
KR (1) KR20180013924A (enExample)
CN (1) CN107710173A (enExample)
BR (1) BR112017025625A2 (enExample)
CA (1) CA2983797A1 (enExample)
TW (1) TW201710908A (enExample)
WO (1) WO2016195850A1 (enExample)

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US10509729B2 (en) * 2016-01-13 2019-12-17 Intel Corporation Address translation for scalable virtualization of input/output devices
US10228981B2 (en) 2017-05-02 2019-03-12 Intel Corporation High-performance input-output devices supporting scalable virtualization
US10635654B2 (en) * 2017-06-12 2020-04-28 Samsung Electronics Co., Ltd. Data journaling for large solid state storage devices with low DRAM/SRAM
US10649912B2 (en) * 2017-07-14 2020-05-12 International Business Machines Corporation Method and apparatus for an efficient TLB lookup
US20190087351A1 (en) * 2017-09-20 2019-03-21 Qualcomm Incorporated Transaction dispatcher for memory management unit
US10628072B2 (en) * 2018-08-21 2020-04-21 Samsung Electronics Co., Ltd. Scalable architecture enabling large memory system for in-memory computations
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CN113127064B (zh) * 2019-12-31 2025-02-14 深圳云天励飞技术有限公司 一种并发调度和执行时序数据的方法及相关装置
KR102824954B1 (ko) * 2020-07-24 2025-06-25 한국전자통신연구원 병렬 처리 시스템에서의 메모리 액세스 제어 장치 및 메모리 액세스 제어 방법

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JP7754605B2 (ja) 2021-08-30 2025-10-15 インターナショナル・ビジネス・マシーンズ・コーポレーション 同時アドレス変換テーブルウォークのためのスリープ／ウェイクアップ性能強化

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CA2983797A1 (en) 2016-12-08
EP3304320A1 (en) 2018-04-11
TW201710908A (zh) 2017-03-16
US10007619B2 (en) 2018-06-26
KR20180013924A (ko) 2018-02-07
WO2016195850A1 (en) 2016-12-08
US20160350234A1 (en) 2016-12-01
BR112017025625A2 (pt) 2018-08-07
CN107710173A (zh) 2018-02-16

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