CN107710173A - 用于存储器管理单元的多线程转换及事务重新排序 - Google Patents

用于存储器管理单元的多线程转换及事务重新排序 Download PDF

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Publication number
CN107710173A
CN107710173A CN201680029881.7A CN201680029881A CN107710173A CN 107710173 A CN107710173 A CN 107710173A CN 201680029881 A CN201680029881 A CN 201680029881A CN 107710173 A CN107710173 A CN 107710173A
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CN
China
Prior art keywords
address translation
translation
requests
cache
translation requests
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Pending
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CN201680029881.7A
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English (en)
Chinese (zh)
Inventor
J·E·波达艾玛
P·C·J·维尔齐恩斯基
C·J·摩瑞拉
A·米雷特斯凯
M·瓦里亚
K·J·厄恩魏因
M·索马孙达拉姆
M·U·乔德里
S·M·加代尔拉布
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Qualcomm Inc
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Qualcomm Inc
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Publication of CN107710173A publication Critical patent/CN107710173A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/655—Same page detection
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/682—Multiprocessor TLB consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/683—Invalidation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/684—TLB miss handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201680029881.7A 2015-05-29 2016-04-27 用于存储器管理单元的多线程转换及事务重新排序 Pending CN107710173A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562168712P 2015-05-29 2015-05-29
US62/168,712 2015-05-29
US14/859,351 US10007619B2 (en) 2015-05-29 2015-09-20 Multi-threaded translation and transaction re-ordering for memory management units
US14/859,351 2015-09-20
PCT/US2016/029502 WO2016195850A1 (en) 2015-05-29 2016-04-27 Multi-threaded translation and transaction re-ordering for memory management units

Publications (1)

Publication Number Publication Date
CN107710173A true CN107710173A (zh) 2018-02-16

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Country Link
US (1) US10007619B2 (enExample)
EP (1) EP3304320A1 (enExample)
JP (1) JP2018519581A (enExample)
KR (1) KR20180013924A (enExample)
CN (1) CN107710173A (enExample)
BR (1) BR112017025625A2 (enExample)
CA (1) CA2983797A1 (enExample)
TW (1) TW201710908A (enExample)
WO (1) WO2016195850A1 (enExample)

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US10228981B2 (en) 2017-05-02 2019-03-12 Intel Corporation High-performance input-output devices supporting scalable virtualization
US10635654B2 (en) * 2017-06-12 2020-04-28 Samsung Electronics Co., Ltd. Data journaling for large solid state storage devices with low DRAM/SRAM
US10649912B2 (en) * 2017-07-14 2020-05-12 International Business Machines Corporation Method and apparatus for an efficient TLB lookup
US20190087351A1 (en) * 2017-09-20 2019-03-21 Qualcomm Incorporated Transaction dispatcher for memory management unit
US10628072B2 (en) * 2018-08-21 2020-04-21 Samsung Electronics Co., Ltd. Scalable architecture enabling large memory system for in-memory computations
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CN113127064B (zh) * 2019-12-31 2025-02-14 深圳云天励飞技术有限公司 一种并发调度和执行时序数据的方法及相关装置
KR102824954B1 (ko) * 2020-07-24 2025-06-25 한국전자통신연구원 병렬 처리 시스템에서의 메모리 액세스 제어 장치 및 메모리 액세스 제어 방법
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Also Published As

Publication number Publication date
US20160350234A1 (en) 2016-12-01
KR20180013924A (ko) 2018-02-07
BR112017025625A2 (pt) 2018-08-07
WO2016195850A1 (en) 2016-12-08
TW201710908A (zh) 2017-03-16
CA2983797A1 (en) 2016-12-08
JP2018519581A (ja) 2018-07-19
US10007619B2 (en) 2018-06-26
EP3304320A1 (en) 2018-04-11

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