JP2018519581A5 - - Google Patents

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Publication number
JP2018519581A5
JP2018519581A5 JP2017560966A JP2017560966A JP2018519581A5 JP 2018519581 A5 JP2018519581 A5 JP 2018519581A5 JP 2017560966 A JP2017560966 A JP 2017560966A JP 2017560966 A JP2017560966 A JP 2017560966A JP 2018519581 A5 JP2018519581 A5 JP 2018519581A5
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JP
Japan
Prior art keywords
translation
address translation
address
requests
scheduler
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2017560966A
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English (en)
Japanese (ja)
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JP2018519581A (ja
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Publication date
Priority claimed from US14/859,351 external-priority patent/US10007619B2/en
Application filed filed Critical
Publication of JP2018519581A publication Critical patent/JP2018519581A/ja
Publication of JP2018519581A5 publication Critical patent/JP2018519581A5/ja
Ceased legal-status Critical Current

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JP2017560966A 2015-05-29 2016-04-27 メモリ管理ユニットに対するマルチスレッド変換およびトランザクション並べ替え Ceased JP2018519581A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562168712P 2015-05-29 2015-05-29
US62/168,712 2015-05-29
US14/859,351 2015-09-20
US14/859,351 US10007619B2 (en) 2015-05-29 2015-09-20 Multi-threaded translation and transaction re-ordering for memory management units
PCT/US2016/029502 WO2016195850A1 (en) 2015-05-29 2016-04-27 Multi-threaded translation and transaction re-ordering for memory management units

Publications (2)

Publication Number Publication Date
JP2018519581A JP2018519581A (ja) 2018-07-19
JP2018519581A5 true JP2018519581A5 (enExample) 2018-09-06

Family

ID=57397568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017560966A Ceased JP2018519581A (ja) 2015-05-29 2016-04-27 メモリ管理ユニットに対するマルチスレッド変換およびトランザクション並べ替え

Country Status (9)

Country Link
US (1) US10007619B2 (enExample)
EP (1) EP3304320A1 (enExample)
JP (1) JP2018519581A (enExample)
KR (1) KR20180013924A (enExample)
CN (1) CN107710173A (enExample)
BR (1) BR112017025625A2 (enExample)
CA (1) CA2983797A1 (enExample)
TW (1) TW201710908A (enExample)
WO (1) WO2016195850A1 (enExample)

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US10228981B2 (en) 2017-05-02 2019-03-12 Intel Corporation High-performance input-output devices supporting scalable virtualization
US10635654B2 (en) * 2017-06-12 2020-04-28 Samsung Electronics Co., Ltd. Data journaling for large solid state storage devices with low DRAM/SRAM
US10649912B2 (en) * 2017-07-14 2020-05-12 International Business Machines Corporation Method and apparatus for an efficient TLB lookup
US20190087351A1 (en) * 2017-09-20 2019-03-21 Qualcomm Incorporated Transaction dispatcher for memory management unit
US10628072B2 (en) * 2018-08-21 2020-04-21 Samsung Electronics Co., Ltd. Scalable architecture enabling large memory system for in-memory computations
GB2578099B (en) 2018-10-15 2021-05-12 Advanced Risc Mach Ltd Memory access control
CN113127064B (zh) * 2019-12-31 2025-02-14 深圳云天励飞技术有限公司 一种并发调度和执行时序数据的方法及相关装置
KR102824954B1 (ko) * 2020-07-24 2025-06-25 한국전자통신연구원 병렬 처리 시스템에서의 메모리 액세스 제어 장치 및 메모리 액세스 제어 방법
US11636043B2 (en) * 2021-08-30 2023-04-25 International Business Machines Corporation Sleeping and waking-up address translation that conflicts with translation level of active page table walks

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US7904692B2 (en) * 2007-11-01 2011-03-08 Shrijeet Mukherjee Iommu with translation request management and methods for managing translation requests
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US8108584B2 (en) * 2008-10-15 2012-01-31 Intel Corporation Use of completer knowledge of memory region ordering requirements to modify transaction attributes
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CN103348333B (zh) * 2011-12-23 2017-03-29 英特尔公司 用于分级高速缓存设计中的高速缓存之间的高效通信的方法和装置
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