BR112015019103A2 - erros de memória incorrigíveis reduzidos - Google Patents

erros de memória incorrigíveis reduzidos

Info

Publication number
BR112015019103A2
BR112015019103A2 BR112015019103A BR112015019103A BR112015019103A2 BR 112015019103 A2 BR112015019103 A2 BR 112015019103A2 BR 112015019103 A BR112015019103 A BR 112015019103A BR 112015019103 A BR112015019103 A BR 112015019103A BR 112015019103 A2 BR112015019103 A2 BR 112015019103A2
Authority
BR
Brazil
Prior art keywords
memory
array
reduced
memory errors
uncorrectable memory
Prior art date
Application number
BR112015019103A
Other languages
English (en)
Other versions
BR112015019103B1 (pt
Inventor
Rivers Doyle
m walker Julie
Pangal Kiran
S Damle Prashant
Sundaram Rajesh
Qawami Shekoufeh
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112015019103A2 publication Critical patent/BR112015019103A2/pt
Publication of BR112015019103B1 publication Critical patent/BR112015019103B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Quality & Reliability (AREA)
  • Human Computer Interaction (AREA)
  • Computer Security & Cryptography (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Mathematical Physics (AREA)
  • Algebra (AREA)
  • Pure & Applied Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

resumo patente de invenção: "erros de memória incorrigíveis reduzidos". a presente invenção refere-se a erros de memória incorrigíveis que podem ser reduzidos determinando-se um endereço de arranjo lógico para um conjunto de arranjos de memória e transformando-se o endereço de arranjo lógico em pelo menos dois endereços de arranjo únicos com base, pelo menos em parte, em localizações lógicas de pelo menos dois arranjos de memória dentro do conjunto de arranjos de memória. os pelo menos dois arranjos de memória são, então, acessados com o uso dos pelo menos dois endereços de arranjo únicos, respectivamente.
BR112015019103-7A 2013-03-11 2014-03-05 Método para reduzir erros de memória incorrigíveis, circuito integrado e sistema eletrônico BR112015019103B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/792,597 US9136873B2 (en) 2013-03-11 2013-03-11 Reduced uncorrectable memory errors
US13/792,597 2013-03-11
PCT/US2014/020549 WO2014164099A1 (en) 2013-03-11 2014-03-05 Reduced uncorrectable memory errors

Publications (2)

Publication Number Publication Date
BR112015019103A2 true BR112015019103A2 (pt) 2017-07-18
BR112015019103B1 BR112015019103B1 (pt) 2022-05-17

Family

ID=51489439

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015019103-7A BR112015019103B1 (pt) 2013-03-11 2014-03-05 Método para reduzir erros de memória incorrigíveis, circuito integrado e sistema eletrônico

Country Status (7)

Country Link
US (4) US9136873B2 (pt)
EP (2) EP3282361A1 (pt)
JP (2) JP6087470B2 (pt)
KR (1) KR101693664B1 (pt)
CN (1) CN104969193B (pt)
BR (1) BR112015019103B1 (pt)
WO (1) WO2014164099A1 (pt)

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US9136873B2 (en) 2013-03-11 2015-09-15 Intel Corporation Reduced uncorrectable memory errors
KR101767018B1 (ko) * 2013-09-27 2017-08-09 인텔 코포레이션 비휘발성 메모리에서의 오류 정정
US9478315B2 (en) * 2014-06-03 2016-10-25 Sandisk Technologies Llc Bit error rate mapping in a memory system
US10438658B2 (en) 2014-12-26 2019-10-08 Intel Corporation Refresh logic to refresh only memory cells having a first value
US9672905B1 (en) * 2016-07-22 2017-06-06 Pure Storage, Inc. Optimize data protection layouts based on distributed flash wear leveling
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US10831596B2 (en) * 2018-01-22 2020-11-10 Micron Technology, Inc. Enhanced error correcting code capability using variable logical to physical associations of a data block
US10846175B2 (en) * 2018-04-10 2020-11-24 Micron Technology, Inc. High throughput bit correction of data inside a word buffer for a product code decoder
US10761918B2 (en) 2018-04-18 2020-09-01 International Business Machines Corporation Method to handle corrected memory errors on kernel text
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Also Published As

Publication number Publication date
JP6240351B2 (ja) 2017-11-29
US20180253355A1 (en) 2018-09-06
US9136873B2 (en) 2015-09-15
JP2017117480A (ja) 2017-06-29
US20190370112A1 (en) 2019-12-05
US20160188409A1 (en) 2016-06-30
CN104969193B (zh) 2017-01-18
BR112015019103B1 (pt) 2022-05-17
CN104969193A (zh) 2015-10-07
EP2972876A4 (en) 2016-11-23
WO2014164099A1 (en) 2014-10-09
JP2016514327A (ja) 2016-05-19
US9934088B2 (en) 2018-04-03
EP2972876B1 (en) 2017-12-20
US10936418B2 (en) 2021-03-02
US10324793B2 (en) 2019-06-18
KR20150106916A (ko) 2015-09-22
US20140258804A1 (en) 2014-09-11
JP6087470B2 (ja) 2017-03-01
EP2972876A1 (en) 2016-01-20
KR101693664B1 (ko) 2017-01-06
EP3282361A1 (en) 2018-02-14

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B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

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