BR112015017103A2 - métodos e aparelhos para cancelar dadas solicitações de pré-busca de dados para um loop - Google Patents

métodos e aparelhos para cancelar dadas solicitações de pré-busca de dados para um loop

Info

Publication number
BR112015017103A2
BR112015017103A2 BR112015017103A BR112015017103A BR112015017103A2 BR 112015017103 A2 BR112015017103 A2 BR 112015017103A2 BR 112015017103 A BR112015017103 A BR 112015017103A BR 112015017103 A BR112015017103 A BR 112015017103A BR 112015017103 A2 BR112015017103 A2 BR 112015017103A2
Authority
BR
Brazil
Prior art keywords
prefetch
loop
data
requests
cancel
Prior art date
Application number
BR112015017103A
Other languages
English (en)
Other versions
BR112015017103B1 (pt
Inventor
M Gilbert Matthew
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112015017103A2 publication Critical patent/BR112015017103A2/pt
Publication of BR112015017103B1 publication Critical patent/BR112015017103B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30065—Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G06F9/3455—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results using stride
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

1/1 resumo “métodos e aparelhos para cancelar dadas solicitações de pré-busca de dados para um loop” técnicas eficientes para a redução da poluição de cache através do uso de uma lógica de pré-busca que reconhece as saídas a partir de loops de software ou retornos de função para cancelar quaisquer operações de solicitação de pré-busca pendentes são descritas. a lógica de pré-busca inclui um monitor de endereço de dados de loop para determinar um encaminhamento de acesso de dados com base na execução repetida de uma instrução de acesso à memória em um loop de programa. lógica de pré-busca de dados, em seguida, especulativamente emite as solicitações de pré-busca de acordo com o encaminhamento de acesso de dados. um circuito de pré-busca de parada é utilizado para cancelar solicitações de pré-busca pendentes em resposta a uma saída de loop identificada. a lógica de pré-busca também pode reconhecer um retorno de uma função de chamada e cancelar quaisquer operações de solicitação de pré-busca pendentes associadas à função de chamada. quando as solicitações de pré-busca são canceladas, solicitações de demanda, tal como baseadas nas instruções de carga, não são canceladas. esta abordagem para reduzir a poluição de cache usa informações de fluxo de programa para estrangular a pré-busca de cache de dados.
BR112015017103-6A 2013-01-21 2014-01-18 Método e aparelho para cancelar solicitações de pré-busca de dados para um loop BR112015017103B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/746,000 2013-01-21
US13/746,000 US9519586B2 (en) 2013-01-21 2013-01-21 Methods and apparatus to reduce cache pollution caused by data prefetching
PCT/US2014/012152 WO2014113741A1 (en) 2013-01-21 2014-01-18 Methods and apparatus for cancelling data prefetch requests for a loop

Publications (2)

Publication Number Publication Date
BR112015017103A2 true BR112015017103A2 (pt) 2017-07-11
BR112015017103B1 BR112015017103B1 (pt) 2022-01-11

Family

ID=50113017

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015017103-6A BR112015017103B1 (pt) 2013-01-21 2014-01-18 Método e aparelho para cancelar solicitações de pré-busca de dados para um loop

Country Status (10)

Country Link
US (1) US9519586B2 (pt)
EP (1) EP2946286B1 (pt)
JP (1) JP6143886B2 (pt)
KR (1) KR101788683B1 (pt)
CN (1) CN105074655B (pt)
BR (1) BR112015017103B1 (pt)
ES (1) ES2655852T3 (pt)
HU (1) HUE035210T2 (pt)
TW (1) TWI521347B (pt)
WO (1) WO2014113741A1 (pt)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9348754B2 (en) 2012-10-11 2016-05-24 Soft Machines Inc. Systems and methods for implementing weak stream software data and instruction prefetching using a hardware data prefetcher
US9424046B2 (en) * 2012-10-11 2016-08-23 Soft Machines Inc. Systems and methods for load canceling in a processor that is connected to an external interconnect fabric
CN104133691B (zh) * 2014-05-05 2016-08-31 腾讯科技（深圳）有限公司 加速启动的方法及装置
US20160283243A1 (en) * 2015-03-28 2016-09-29 Yong-Kyu Jung Branch look-ahead instruction disassembling, assembling, and delivering system apparatus and method for microprocessor system
WO2017006235A1 (en) * 2015-07-09 2017-01-12 Centipede Semi Ltd. Processor with efficient memory access
US10275249B1 (en) * 2015-10-15 2019-04-30 Marvell International Ltd. Method and apparatus for predicting end of loop
US10528352B2 (en) 2016-03-08 2020-01-07 International Business Machines Corporation Blocking instruction fetching in a computer processor
US10175987B2 (en) 2016-03-17 2019-01-08 International Business Machines Corporation Instruction prefetching in a computer processor using a prefetch prediction vector
US10474578B2 (en) * 2017-08-30 2019-11-12 Oracle International Corporation Utilization-based throttling of hardware prefetchers
GB2572954B (en) * 2018-04-16 2020-12-30 Advanced Risc Mach Ltd An apparatus and method for prefetching data items
US10649777B2 (en) * 2018-05-14 2020-05-12 International Business Machines Corporation Hardware-based data prefetching based on loop-unrolled instructions
GB2574270B (en) * 2018-06-01 2020-09-09 Advanced Risc Mach Ltd Speculation-restricted memory region type
US11216279B2 (en) * 2018-11-26 2022-01-04 Advanced Micro Devices, Inc. Loop exit predictor
US10884749B2 (en) 2019-03-26 2021-01-05 International Business Machines Corporation Control of speculative demand loads
US10963388B2 (en) * 2019-06-24 2021-03-30 Samsung Electronics Co., Ltd. Prefetching in a lower level exclusive cache hierarchy
CN110442382B (zh) * 2019-07-31 2021-06-15 西安芯海微电子科技有限公司 预取缓存控制方法、装置、芯片以及计算机可读存储介质
US11150812B2 (en) * 2019-08-20 2021-10-19 Micron Technology, Inc. Predictive memory management
CN111541722B (zh) * 2020-05-22 2022-03-18 哈尔滨工程大学 基于密度聚类的信息中心网络缓存污染攻击检测防御方法
US11630654B2 (en) * 2021-08-19 2023-04-18 International Business Machines Corporation Analysis for modeling data cache utilization

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02287828A (ja) * 1989-04-28 1990-11-27 Fujitsu Ltd プリフェッチ制御方式
JPH0439733A (ja) * 1990-06-06 1992-02-10 Fujitsu Ltd 先行制御方式
JPH04344935A (ja) * 1991-05-23 1992-12-01 Nec Corp 情報処理装置
JPH10232775A (ja) * 1997-02-20 1998-09-02 Hitachi Ltd プリフェッチ機構
US5996061A (en) * 1997-06-25 1999-11-30 Sun Microsystems, Inc. Method for invalidating data identified by software compiler
US6430680B1 (en) 1998-03-31 2002-08-06 International Business Machines Corporation Processor and method of prefetching data based upon a detected stride
US6260116B1 (en) 1998-07-01 2001-07-10 International Business Machines Corporation System and method for prefetching data
US6611910B2 (en) * 1998-10-12 2003-08-26 Idea Corporation Method for processing branch operations
US6446143B1 (en) * 1998-11-25 2002-09-03 Compaq Information Technologies Group, L.P. Methods and apparatus for minimizing the impact of excessive instruction retrieval
US6321330B1 (en) 1999-05-28 2001-11-20 Intel Corporation Each iteration array selective loop data prefetch in multiple data width prefetch system using rotating register and parameterization to avoid redundant prefetch
US6799263B1 (en) * 1999-10-28 2004-09-28 Hewlett-Packard Development Company, L.P. Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted
US6775765B1 (en) * 2000-02-07 2004-08-10 Freescale Semiconductor, Inc. Data processing system having instruction folding and method thereof
US20020144054A1 (en) * 2001-03-30 2002-10-03 Fanning Blaise B. Prefetch canceling based on most recent accesses
JP3683248B2 (ja) * 2002-10-22 2005-08-17 富士通株式会社 情報処理装置及び情報処理方法
US7194582B1 (en) 2003-05-30 2007-03-20 Mips Technologies, Inc. Microprocessor with improved data stream prefetching
US7526604B1 (en) 2004-08-09 2009-04-28 Nvidia Corporation Command queueing speculative write prefetch
US7587580B2 (en) * 2005-02-03 2009-09-08 Qualcomm Corporated Power efficient instruction prefetch mechanism
US8589666B2 (en) 2006-07-10 2013-11-19 Src Computers, Inc. Elimination of stream consumer loop overshoot effects
US7917701B2 (en) * 2007-03-12 2011-03-29 Arm Limited Cache circuitry, data processing apparatus and method for prefetching data by selecting one of a first prefetch linefill operation and a second prefetch linefill operation
US7640420B2 (en) * 2007-04-02 2009-12-29 Intel Corporation Pre-fetch apparatus
GB0722707D0 (en) 2007-11-19 2007-12-27 St Microelectronics Res & Dev Cache memory
US8479053B2 (en) 2010-07-28 2013-07-02 Intel Corporation Processor with last branch record register storing transaction indicator
US8661169B2 (en) 2010-09-15 2014-02-25 Lsi Corporation Copying data to a cache using direct memory access
US9009414B2 (en) 2010-09-21 2015-04-14 Texas Instruments Incorporated Prefetch address hit prediction to reduce memory access latency

Also Published As

Publication number Publication date
KR101788683B1 (ko) 2017-10-20
CN105074655B (zh) 2018-04-06
KR20150110588A (ko) 2015-10-02
US20140208039A1 (en) 2014-07-24
WO2014113741A1 (en) 2014-07-24
BR112015017103B1 (pt) 2022-01-11
CN105074655A (zh) 2015-11-18
TW201443645A (zh) 2014-11-16
JP2016507836A (ja) 2016-03-10
US9519586B2 (en) 2016-12-13
HUE035210T2 (hu) 2018-05-02
ES2655852T3 (es) 2018-02-21
EP2946286B1 (en) 2017-10-25
EP2946286A1 (en) 2015-11-25
JP6143886B2 (ja) 2017-06-07
TWI521347B (zh) 2016-02-11

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Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 18/01/2014, OBSERVADAS AS CONDICOES LEGAIS.