BR112015030066A2 - processadores, métodos e sistemas para acessar um conjunto de registradores como uma pluralidade de registradores menores ou como um registrador maior combinado - Google Patents

processadores, métodos e sistemas para acessar um conjunto de registradores como uma pluralidade de registradores menores ou como um registrador maior combinado

Info

Publication number
BR112015030066A2
BR112015030066A2 BR112015030066A BR112015030066A BR112015030066A2 BR 112015030066 A2 BR112015030066 A2 BR 112015030066A2 BR 112015030066 A BR112015030066 A BR 112015030066A BR 112015030066 A BR112015030066 A BR 112015030066A BR 112015030066 A2 BR112015030066 A2 BR 112015030066A2
Authority
BR
Brazil
Prior art keywords
register
registers
accessing
processors
systems
Prior art date
Application number
BR112015030066A
Other languages
English (en)
Inventor
L Toll Bret
M Guy Buford
Naik Mishali
Singhal Ronak
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112015030066A2 publication Critical patent/BR112015030066A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30192—Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

“processadores, métodos e sistemas para acessar um conjunto de registradores como uma pluralidade de registradores menores ou como um registrador maior combinado” trata-se de um processador de um aspecto que inclui um conjunto de registradores que têm a capacidade de armazenar dados compactados. uma unidade de execução é acoplada ao conjunto de registradores. a unidade de execução deve acessar o conjunto de registradores de pelo menos duas maneiras diferentes em resposta a instruções. as pelo menos duas maneiras diferentes incluem uma primeira maneira na qual o conjunto de registradores deve representar uma pluralidade de registradores de n bits. as pelo menos duas maneiras diferentes incluem, ainda, uma segunda maneira na qual o conjunto de registradores deve representar um registrador único de pelo menos 2n bits. em um aspecto, os pelo menos 2n bits devem ser pelo menos 256 bits.
BR112015030066A 2013-06-28 2014-06-26 processadores, métodos e sistemas para acessar um conjunto de registradores como uma pluralidade de registradores menores ou como um registrador maior combinado BR112015030066A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/931,047 US10228941B2 (en) 2013-06-28 2013-06-28 Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register
PCT/US2014/044389 WO2014210345A1 (en) 2013-06-28 2014-06-26 Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register

Publications (1)

Publication Number Publication Date
BR112015030066A2 true BR112015030066A2 (pt) 2017-07-25

Family

ID=52116854

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015030066A BR112015030066A2 (pt) 2013-06-28 2014-06-26 processadores, métodos e sistemas para acessar um conjunto de registradores como uma pluralidade de registradores menores ou como um registrador maior combinado

Country Status (8)

Country Link
US (1) US10228941B2 (pt)
EP (1) EP3014419A4 (pt)
KR (1) KR101856833B1 (pt)
CN (1) CN105264489B (pt)
BR (1) BR112015030066A2 (pt)
RU (1) RU2639695C2 (pt)
TW (1) TWI599948B (pt)
WO (1) WO2014210345A1 (pt)

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US20170192789A1 (en) * 2015-12-30 2017-07-06 Rama Kishnan V. Malladi Systems, Methods, and Apparatuses for Improving Vector Throughput
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CN108416431B (zh) * 2018-01-19 2021-06-01 上海兆芯集成电路有限公司 神经网络微处理器与宏指令处理方法

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Also Published As

Publication number Publication date
RU2015151125A (ru) 2017-06-01
US10228941B2 (en) 2019-03-12
EP3014419A4 (en) 2017-02-22
US20150006865A1 (en) 2015-01-01
TW201523437A (zh) 2015-06-16
WO2014210345A1 (en) 2014-12-31
CN105264489A (zh) 2016-01-20
TWI599948B (zh) 2017-09-21
EP3014419A1 (en) 2016-05-04
KR20150141994A (ko) 2015-12-21
CN105264489B (zh) 2019-06-25
KR101856833B1 (ko) 2018-05-10
RU2639695C2 (ru) 2017-12-21

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements
B350 Update of information on the portal [chapter 15.35 patent gazette]