BR112018067341A2 - alocação de gravação para cache baseada em permissões de execução - Google Patents

alocação de gravação para cache baseada em permissões de execução

Info

Publication number
BR112018067341A2
BR112018067341A2 BR112018067341A BR112018067341A BR112018067341A2 BR 112018067341 A2 BR112018067341 A2 BR 112018067341A2 BR 112018067341 A BR112018067341 A BR 112018067341A BR 112018067341 A BR112018067341 A BR 112018067341A BR 112018067341 A2 BR112018067341 A2 BR 112018067341A2
Authority
BR
Brazil
Prior art keywords
write
cache
execute
permissions
execute permissions
Prior art date
Application number
BR112018067341A
Other languages
English (en)
Inventor
Norris Dieffenderfer James
Todd Bridges Jeffrey
Alan Dockser Kenneth
Scott Mcilvaine Michael
William Morrow Michael
Wayne Smith Rodney
Andrew Sartorius Thomas
Philip Speier Thomas
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018067341A2 publication Critical patent/BR112018067341A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/604—Details relating to cache allocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6042—Allocation of cache space to multiple users or processors
    • G06F2212/6046—Using a specific cache allocation policy other than replacement policy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/684—TLB miss handling

Abstract

sistemas e métodos para gerenciar o acesso a um cache referem-se à determinação de uma ou mais permissões de execução associadas a um endereço de gravação de uma solicitação de gravação ao cache. o cache pode ser um cache unificado para armazenar dados, assim como instruções. se houver uma perda de gravação no cache para a solicitação de gravação, o controlador de cache pode determinar se será implementa uma política de alocação de gravação ou uma política sem alocação de gravação para servir a perda de gravação, com base na permissão ou permissões de execução. a permissão ou permissões de execução podem referir-se a um nível de privilégio associado ao endereço de gravação. as permissões de execução de um agente produtor que gerou a solicitação de gravação e uma permissão de execução de um agente consumidor que pode ser executado a partir do endereço de gravação podem ser baseadas nos níveis de privilégio do agente produtor e do agente consumidor, respectivamente.
BR112018067341A 2016-03-01 2017-02-08 alocação de gravação para cache baseada em permissões de execução BR112018067341A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/057,121 US20170255569A1 (en) 2016-03-01 2016-03-01 Write-allocation for a cache based on execute permissions
PCT/US2017/016971 WO2017151280A1 (en) 2016-03-01 2017-02-08 Write-allocation for a cache based on execute permissions

Publications (1)

Publication Number Publication Date
BR112018067341A2 true BR112018067341A2 (pt) 2019-01-08

Family

ID=58018350

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018067341A BR112018067341A2 (pt) 2016-03-01 2017-02-08 alocação de gravação para cache baseada em permissões de execução

Country Status (11)

Country Link
US (1) US20170255569A1 (pt)
EP (1) EP3423946B1 (pt)
JP (1) JP6960933B2 (pt)
KR (1) KR20180117629A (pt)
CN (1) CN108604210B (pt)
BR (1) BR112018067341A2 (pt)
ES (1) ES2903162T3 (pt)
HK (1) HK1254828A1 (pt)
SG (1) SG11201806067SA (pt)
TW (1) TW201734807A (pt)
WO (1) WO2017151280A1 (pt)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10114768B2 (en) * 2016-08-29 2018-10-30 Intel Corporation Enhance memory access permission based on per-page current privilege level
US10713177B2 (en) 2016-09-09 2020-07-14 Intel Corporation Defining virtualized page attributes based on guest page attributes
US11010309B2 (en) * 2018-05-18 2021-05-18 Intel Corporation Computer system and method for executing one or more software applications, host computer device and method for a host computer device, memory device and method for a memory device and non-transitory computer readable medium
CN111124267B (zh) * 2018-10-31 2023-10-31 伊姆西Ip控股有限责任公司 数据写入的方法、设备和计算机程序产品
CN112559389A (zh) * 2019-09-25 2021-03-26 阿里巴巴集团控股有限公司 存储控制装置、处理装置、计算机系统和存储控制方法
CN114616552A (zh) * 2019-11-29 2022-06-10 华为技术有限公司 缓存存储器和分配写操作的方法
CN111831587A (zh) * 2020-04-17 2020-10-27 北京奕斯伟计算技术有限公司 数据写入方法、装置和电子设备
US20230418753A1 (en) * 2022-06-28 2023-12-28 Advanced Micro Devices, Inc. Allocation control for cache

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5606687A (en) * 1993-10-07 1997-02-25 Sun Microsystems, Inc. Method and apparatus for optimizing supervisor mode store operations in a data cache
EP0651332B1 (en) * 1993-10-29 2001-07-18 Advanced Micro Devices, Inc. Linearly addressable microprocessor cache
US6119151A (en) * 1994-03-07 2000-09-12 International Business Machines Corp. System and method for efficient cache management in a distributed file system
US6263407B1 (en) * 1998-02-17 2001-07-17 International Business Machines Corporation Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode
JP2000215102A (ja) * 1998-09-01 2000-08-04 Texas Instr Inc <Ti> プロセッサ用の進歩したメモリ階層構造
US6412043B1 (en) * 1999-10-01 2002-06-25 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
JP2003044358A (ja) * 2001-07-31 2003-02-14 Mitsubishi Electric Corp キャッシュメモリ制御装置
EP1304620A1 (en) * 2001-10-17 2003-04-23 Texas Instruments Incorporated Cache with selective write allocation
US6990502B2 (en) * 2003-02-26 2006-01-24 Microsoft Corporation Reviewing cached user-group information in connection with issuing a digital rights management (DRM) license for content
US7437510B2 (en) * 2005-09-30 2008-10-14 Intel Corporation Instruction-assisted cache management for efficient use of cache and memory
US20070079070A1 (en) * 2005-09-30 2007-04-05 Arm Limited Cache controller
US7805588B2 (en) * 2005-10-20 2010-09-28 Qualcomm Incorporated Caching memory attribute indicators with cached memory data field
US8606998B2 (en) * 2006-08-24 2013-12-10 Advanced Micro Devices, Inc. System and method for instruction-based cache allocation policies
US8275971B2 (en) * 2008-08-27 2012-09-25 International Business Machines Corporation Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities
US8621184B1 (en) * 2008-10-31 2013-12-31 Netapp, Inc. Effective scheduling of producer-consumer processes in a multi-processor system
US8621149B2 (en) * 2009-12-23 2013-12-31 Intel Corporation Controlling access to a cache memory using privilege level information
US8504777B2 (en) * 2010-09-21 2013-08-06 Freescale Semiconductor, Inc. Data processor for processing decorated instructions with cache bypass
US20130179642A1 (en) * 2012-01-10 2013-07-11 Qualcomm Incorporated Non-Allocating Memory Access with Physical Address
US9158685B2 (en) * 2012-09-11 2015-10-13 Apple Inc. System cache with cache hint control
US8819342B2 (en) * 2012-09-26 2014-08-26 Qualcomm Incorporated Methods and apparatus for managing page crossing instructions with different cacheability
GB2526849B (en) * 2014-06-05 2021-04-14 Advanced Risc Mach Ltd Dynamic cache allocation policy adaptation in a data processing apparatus
US9335943B2 (en) * 2014-06-30 2016-05-10 Intel Corporation Method and apparatus for fine grain memory protection
US9767040B2 (en) * 2015-08-31 2017-09-19 Salesforce.Com, Inc. System and method for generating and storing real-time analytics metric data using an in memory buffer service consumer framework

Also Published As

Publication number Publication date
ES2903162T3 (es) 2022-03-31
KR20180117629A (ko) 2018-10-29
CN108604210B (zh) 2022-08-19
SG11201806067SA (en) 2018-09-27
EP3423946A1 (en) 2019-01-09
WO2017151280A1 (en) 2017-09-08
TW201734807A (zh) 2017-10-01
JP6960933B2 (ja) 2021-11-05
US20170255569A1 (en) 2017-09-07
JP2019511045A (ja) 2019-04-18
CN108604210A (zh) 2018-09-28
EP3423946B1 (en) 2021-12-15
HK1254828A1 (zh) 2019-07-26

Similar Documents

Publication Publication Date Title
BR112018067341A2 (pt) alocação de gravação para cache baseada em permissões de execução
JP2014526729A5 (pt)
US10162765B2 (en) Routing direct memory access requests in a virtualized computing environment
GB2467499A (en) Automatic optimization for virtual systems
GB2467502A (en) Compliance-based adaptations in managed virtual systems
BR112016021216A2 (pt) instrução de fim de transação condicional
JP2015090615A5 (pt)
BR112015017103A2 (pt) métodos e aparelhos para cancelar dadas solicitações de pré-busca de dados para um loop
JP2017502435A5 (pt)
BR112017026590A2 (pt) técnicas para monitorar dados para mitigar problema transitivo em contextos orientados a objeto
GB2467503A (en) Enforcement of compliance policies in managed virtual systems.
BR112019005604A2 (pt) chip de processador e dispositivo terminal
GB201211422D0 (en) Memory protection
WO2008054996A3 (en) Compliance-based adaptations in managed virtual systems
WO2008049005A3 (en) Automatic optimization for virtual systems
GB2467712A (en) Control and mangement of virtual systems
BR112016007492A8 (pt) método e aparelho para otimização de recurso de memória
ATE509317T1 (de) Verfahren und vorrichtung zur bereitstellung von unabhängigem logischem adressenraum und zugangsverwaltung
WO2013148440A3 (en) Managing coherent memory between an accelerated processing device and a central processing unit
WO2008054997A3 (en) Control and management of virtual systems
WO2011163001A3 (en) Shared data collections
BR112014030364A8 (pt) sistema de plataforma multicamada para acessar pelo menos uma imagem virtual usada por pelo menos uma máquina virtual e método para gerenciar uma plataforma multicamada a acessar pelo menos uma imagem virtual usada por pelo menos uma máquina virtual
RU2015145292A (ru) Управление доступом во время выполнения к интерфейсам прикладного программирования
JP2015519654A5 (pt)
BR112018013334A2 (pt) sistemas e métodos para garantir o acesso continuado à mídia de uma lista de reprodução apesar das restrições de conteúdo geográfico

Legal Events

Date Code Title Description
B350 Update of information on the portal [chapter 15.35 patent gazette]
B06W Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette]