CN114616552A - 缓存存储器和分配写操作的方法 - Google Patents
缓存存储器和分配写操作的方法 Download PDFInfo
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- CN114616552A CN114616552A CN201980101851.6A CN201980101851A CN114616552A CN 114616552 A CN114616552 A CN 114616552A CN 201980101851 A CN201980101851 A CN 201980101851A CN 114616552 A CN114616552 A CN 114616552A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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Abstract
本申请实施例公开了缓存存储器和分配写操作的方法,涉及存储技术领域,能够减小对SW采用静态的策略控制写分配或写不分配造成的缓存性能下降的影响。该缓存存储器包括:探测器,用于从接收的写操作中探测到目标写操作流,目标写操作流中所包含的多个写操作的地址具有规律性,目标写操作流是指对全修改缓存行进行的写操作;寄存器,用于存储至少一个历史写操作流的信息,至少一个历史写操作流用于指示目标写操作流之前的写操作流;仲裁器,用于根据历史写操作流的信息确定是否为目标写操作流分配缓存行。本申请实施例用于确定是否为写操作流分配缓存行。
Description
PCT国内申请,说明书已公开。
Claims (18)
- PCT国内申请,权利要求书已公开。
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PCT/CN2019/122226 WO2021103020A1 (zh) | 2019-11-29 | 2019-11-29 | 缓存存储器和分配写操作的方法 |
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CN114616552A true CN114616552A (zh) | 2022-06-10 |
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CN201980101851.6A Pending CN114616552A (zh) | 2019-11-29 | 2019-11-29 | 缓存存储器和分配写操作的方法 |
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WO (1) | WO2021103020A1 (zh) |
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Publication number | Priority date | Publication date | Assignee | Title |
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US8904115B2 (en) * | 2010-09-28 | 2014-12-02 | Texas Instruments Incorporated | Cache with multiple access pipelines |
CN102053929A (zh) * | 2010-12-17 | 2011-05-11 | 天津曙光计算机产业有限公司 | 一种基于Linux系统DM层的IO缓存操作方法和系统 |
CN103076992B (zh) * | 2012-12-27 | 2016-09-28 | 杭州华为数字技术有限公司 | 一种内存数据缓冲方法及装置 |
GB2526849B (en) * | 2014-06-05 | 2021-04-14 | Advanced Risc Mach Ltd | Dynamic cache allocation policy adaptation in a data processing apparatus |
US20170255569A1 (en) * | 2016-03-01 | 2017-09-07 | Qualcomm Incorporated | Write-allocation for a cache based on execute permissions |
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- 2019-11-29 WO PCT/CN2019/122226 patent/WO2021103020A1/zh active Application Filing
- 2019-11-29 CN CN201980101851.6A patent/CN114616552A/zh active Pending
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