BR112016024376A2 - ?método para desabilitar e habilitar sinais de relógio, circuito de geração de relógio operativo, e, dispositivo de comunicação sem fio? - Google Patents

?método para desabilitar e habilitar sinais de relógio, circuito de geração de relógio operativo, e, dispositivo de comunicação sem fio?

Info

Publication number
BR112016024376A2
BR112016024376A2 BR112016024376A BR112016024376A BR112016024376A2 BR 112016024376 A2 BR112016024376 A2 BR 112016024376A2 BR 112016024376 A BR112016024376 A BR 112016024376A BR 112016024376 A BR112016024376 A BR 112016024376A BR 112016024376 A2 BR112016024376 A2 BR 112016024376A2
Authority
BR
Brazil
Prior art keywords
clock
clock signal
clock signals
synchronization
phase
Prior art date
Application number
BR112016024376A
Other languages
English (en)
Other versions
BR112016024376A8 (pt
BR112016024376B1 (pt
Inventor
Kohola Jukka
Pessa Marko
Lintonen Mikko
Varkki Olli
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR112016024376A2 publication Critical patent/BR112016024376A2/pt
Publication of BR112016024376A8 publication Critical patent/BR112016024376A8/pt
Publication of BR112016024376B1 publication Critical patent/BR112016024376B1/pt

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00286—Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

um circuito de geração do relógio é operativo para desabilitar e habilitar uma pluralidade de sinais de relógio de saída mantendo ainda relacionamentos de fase predeterminados entre os sinais de relógio. um sinal de relógio de referência é dividido por um fator de pelo menos dois, para gerar um sinal de relógio mestre. uma pluralidade de circuitos de fase, cada qual independentemente habilitado, gera uma pluralidade de sinais de relógio de saída dividindo o sinal de relógio de referência. os sinais de relógio de saída têm relacionamentos de fase predeterminado relativos um com o outro. cada circuito de fase é habilitado sincronizadamente para uma borda de sincronização do sinal de relógio mestre. um circuito de sincronização associado com cada circuito de fase assegura sincronização com o sinal de relógio mestre produzindo um sinal de habilitação do circuito de fase somente nas condições em que um sinal de habilitação de relógio associado com o relógio de saída é afirmado e um número predeterminado de bordas de sincronização de sinal de relógio mestre é recebido.
BR112016024376-5A 2014-04-24 2015-04-16 Método para desabilitar e habilitar sinais de relógio, circuito de geração de relógio operativo, e, dispositivo de comunicação sem fio BR112016024376B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/260,622 US9118458B1 (en) 2014-04-24 2014-04-24 Clock phase alignment
US14/260622 2014-04-24
PCT/EP2015/058314 WO2015162057A1 (en) 2014-04-24 2015-04-16 Clock phase alignment

Publications (3)

Publication Number Publication Date
BR112016024376A2 true BR112016024376A2 (pt) 2017-08-15
BR112016024376A8 BR112016024376A8 (pt) 2021-06-01
BR112016024376B1 BR112016024376B1 (pt) 2022-09-27

Family

ID=52875700

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112016024376-5A BR112016024376B1 (pt) 2014-04-24 2015-04-16 Método para desabilitar e habilitar sinais de relógio, circuito de geração de relógio operativo, e, dispositivo de comunicação sem fio

Country Status (6)

Country Link
US (1) US9118458B1 (pt)
EP (1) EP3134794B1 (pt)
CN (1) CN107077163B (pt)
BR (1) BR112016024376B1 (pt)
DK (1) DK3134794T3 (pt)
WO (1) WO2015162057A1 (pt)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5880603B2 (ja) * 2014-03-19 2016-03-09 日本電気株式会社 クロック発生装置、サーバシステムおよびクロック制御方法
CN107728706A (zh) * 2017-11-06 2018-02-23 郑州云海信息技术有限公司 一种基于使能时钟树的时钟产生系统
JP7087509B2 (ja) * 2018-03-19 2022-06-21 富士フイルムビジネスイノベーション株式会社 情報処理装置及び回路装置
CN117519425B (zh) * 2024-01-03 2024-05-10 芯耀辉科技有限公司 一种时钟信号生成方法、计算机设备及介质

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JPH04113718A (ja) * 1990-09-04 1992-04-15 Fujitsu Ltd ヒットレス・クロック切替装置
US5471314A (en) * 1993-06-14 1995-11-28 Eastman Kodak Company Line start synchronizer for raster scanner
US6173432B1 (en) * 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US6118314A (en) 1998-10-14 2000-09-12 Vlsi Technology, Inc. Circuit assembly and method of synchronizing plural circuits
US6188286B1 (en) 1999-03-30 2001-02-13 Infineon Technologies North America Corp. Method and system for synchronizing multiple subsystems using one voltage-controlled oscillator
US6333653B1 (en) 1999-11-04 2001-12-25 International Business Machines Corporation System and method for phase alignment of a plurality of clock pulses when starting, stopping and pulsing clocks
US6873195B2 (en) * 2001-08-22 2005-03-29 Bigband Networks Bas, Inc. Compensating for differences between clock signals
US6944780B1 (en) * 2002-01-19 2005-09-13 National Semiconductor Corporation Adaptive voltage scaling clock generator for use in a digital processing component and method of operating the same
US7492793B2 (en) * 2005-10-20 2009-02-17 International Business Machines Corporation Method for controlling asynchronous clock domains to perform synchronous operations
CN101132247B (zh) * 2007-09-28 2011-04-06 中兴通讯股份有限公司 一种实现主备时钟相位对齐的方法及其装置
US7965111B2 (en) 2008-04-29 2011-06-21 Qualcomm Incorporated Method and apparatus for divider unit synchronization
JP2010074201A (ja) * 2008-09-16 2010-04-02 Nec Electronics Corp 同期検出回路、これを用いたパルス幅変調回路、及び同期検出方法
KR101040242B1 (ko) * 2008-10-13 2011-06-09 주식회사 하이닉스반도체 데이터 스트로브 신호 생성장치 및 이를 이용하는 반도체 메모리 장치
CN101599807A (zh) * 2009-06-19 2009-12-09 中兴通讯股份有限公司 一种使主备时钟相位对齐的方法和装置
TWI394026B (zh) * 2010-01-07 2013-04-21 Richtek Technology Corp 時脈產生器以及應用該時脈產生器的相位交錯時脈同步裝置及方法
US8188782B1 (en) 2010-12-12 2012-05-29 Mediatek Inc. Clock system and method for compensating timing information of clock system
CN102361456B (zh) 2011-10-26 2013-07-03 华亚微电子（上海）有限公司 一种时钟相位对齐调整电路
US8810299B2 (en) * 2012-10-09 2014-08-19 Altera Corporation Signal flow control through clock signal rate adjustments
EP2762990B1 (en) * 2013-02-01 2015-12-09 Nxp B.V. Clock selection circuit and method

Also Published As

Publication number Publication date
CN107077163A (zh) 2017-08-18
CN107077163B (zh) 2020-06-09
BR112016024376A8 (pt) 2021-06-01
DK3134794T3 (da) 2021-03-22
BR112016024376B1 (pt) 2022-09-27
US9118458B1 (en) 2015-08-25
EP3134794A1 (en) 2017-03-01
WO2015162057A1 (en) 2015-10-29
EP3134794B1 (en) 2021-02-24

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B350 Update of information on the portal [chapter 15.35 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 16/04/2015, OBSERVADAS AS CONDICOES LEGAIS