BR112016023683A2 - substrato de pacote compreendendo interconexão de superfície e cavidade compreendendo preenchimento não elétrico - Google Patents

substrato de pacote compreendendo interconexão de superfície e cavidade compreendendo preenchimento não elétrico

Info

Publication number
BR112016023683A2
BR112016023683A2 BR112016023683A BR112016023683A BR112016023683A2 BR 112016023683 A2 BR112016023683 A2 BR 112016023683A2 BR 112016023683 A BR112016023683 A BR 112016023683A BR 112016023683 A BR112016023683 A BR 112016023683A BR 112016023683 A2 BR112016023683 A2 BR 112016023683A2
Authority
BR
Brazil
Prior art keywords
layer
interconnect
dielectric layer
cavity
package substrate
Prior art date
Application number
BR112016023683A
Other languages
English (en)
Inventor
Kim Chin-Kwan
Wafic Jomaa Houssam
James Bchir Omar
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112016023683A2 publication Critical patent/BR112016023683A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/422—Plated through-holes or plated via connections characterised by electroless plating method; pretreatment therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0344—Electroless sublayer, e.g. Ni, Co, Cd or Ag; Transferred electroless sublayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers

Abstract

algumas características inovadoras referem-se a um substrato que inclui uma primeira camada dielétrica, uma primeira interconexão, uma primeira cavidade, e uma primeira camada de metal não elétrico. a primeira camada dielétrica inclui uma primeira superfície e uma segunda superfície. a primeira interconexão está na primeira superfície da camada de substrato. a primeira cavidade atravessa a primeira superfície da primeira camada dielétrica. a primeira camada de metal não elétrico é formada pelo menos parcialmente na primeira cavidade. a primeira camada de metal não elétrico define uma segunda interconexão incorporada na primeira camada dielétrica. em algumas implementações, o substrato inclui ainda uma camada central. a camada central inclui uma primeira superfície e uma segunda superfície. a primeira superfície da camada central é acoplada à segunda superfície da primeira camada dielétrica. em algumas implementações, o substrato inclui ainda uma segunda camada dielétrica.
BR112016023683A 2014-04-11 2015-04-09 substrato de pacote compreendendo interconexão de superfície e cavidade compreendendo preenchimento não elétrico BR112016023683A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/251,486 US9609751B2 (en) 2014-04-11 2014-04-11 Package substrate comprising surface interconnect and cavity comprising electroless fill
PCT/US2015/025150 WO2015157536A1 (en) 2014-04-11 2015-04-09 Package substrate comprising surface interconnect and cavity comprising electroless fill

Publications (1)

Publication Number Publication Date
BR112016023683A2 true BR112016023683A2 (pt) 2017-08-15

Family

ID=52998260

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112016023683A BR112016023683A2 (pt) 2014-04-11 2015-04-09 substrato de pacote compreendendo interconexão de superfície e cavidade compreendendo preenchimento não elétrico

Country Status (7)

Country Link
US (1) US9609751B2 (pt)
EP (1) EP3130007B1 (pt)
JP (1) JP6240342B2 (pt)
KR (1) KR101831643B1 (pt)
CN (1) CN106165093B (pt)
BR (1) BR112016023683A2 (pt)
WO (1) WO2015157536A1 (pt)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITUB20155408A1 (it) * 2015-11-10 2017-05-10 St Microelectronics Srl Substrato di packaging per dispositivi a semiconduttore, dispositivo e procedimento corrispondenti
EP3373714B1 (en) * 2017-03-08 2023-08-23 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Hybrid component carrier and method for manufacturing the same
US20190067178A1 (en) * 2017-08-30 2019-02-28 Qualcomm Incorporated Fine pitch and spacing interconnects with reserve interconnect portion
US11637057B2 (en) * 2019-01-07 2023-04-25 Qualcomm Incorporated Uniform via pad structure having covered traces between partially covered pads
US11410968B2 (en) 2019-10-18 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
CN114900946A (zh) * 2022-03-28 2022-08-12 诚亿电子（嘉兴）有限公司 一种微间距slp类载板及其制备工艺

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Also Published As

Publication number Publication date
US9609751B2 (en) 2017-03-28
JP2017517872A (ja) 2017-06-29
EP3130007B1 (en) 2021-09-29
KR20160144367A (ko) 2016-12-16
JP6240342B2 (ja) 2017-11-29
US20150296616A1 (en) 2015-10-15
KR101831643B1 (ko) 2018-02-23
CN106165093B (zh) 2019-03-05
CN106165093A (zh) 2016-11-23
EP3130007A1 (en) 2017-02-15
WO2015157536A1 (en) 2015-10-15

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B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 5A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2561 DE 04/02/2020.

B350 Update of information on the portal [chapter 15.35 patent gazette]