BE764401A - Montage de circuits d'acces dans des reseaux de circuits integres - Google Patents

Montage de circuits d'acces dans des reseaux de circuits integres

Info

Publication number
BE764401A
BE764401A BE764401A BE764401A BE764401A BE 764401 A BE764401 A BE 764401A BE 764401 A BE764401 A BE 764401A BE 764401 A BE764401 A BE 764401A BE 764401 A BE764401 A BE 764401A
Authority
BE
Belgium
Prior art keywords
mounting
integrated circuit
access circuits
circuit networks
networks
Prior art date
Application number
BE764401A
Other languages
English (en)
Inventor
P R Schroeder
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of BE764401A publication Critical patent/BE764401A/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
BE764401A 1970-03-19 1971-03-17 Montage de circuits d'acces dans des reseaux de circuits integres BE764401A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US2109070A 1970-03-19 1970-03-19

Publications (1)

Publication Number Publication Date
BE764401A true BE764401A (fr) 1971-08-16

Family

ID=21802289

Family Applications (1)

Application Number Title Priority Date Filing Date
BE764401A BE764401A (fr) 1970-03-19 1971-03-17 Montage de circuits d'acces dans des reseaux de circuits integres

Country Status (8)

Country Link
US (1) US3638202A (fr)
JP (1) JPS5116113B1 (fr)
BE (1) BE764401A (fr)
DE (1) DE2113306B2 (fr)
FR (1) FR2083417B1 (fr)
GB (1) GB1322990A (fr)
NL (1) NL7103417A (fr)
SE (1) SE359185B (fr)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1487945A (en) * 1974-11-20 1977-10-05 Ibm Semiconductor integrated circuit devices
US4015159A (en) * 1975-09-15 1977-03-29 Bell Telephone Laboratories, Incorporated Semiconductor integrated circuit transistor detector array for channel electron multiplier
US4161662A (en) * 1976-01-22 1979-07-17 Motorola, Inc. Standardized digital logic chip
JPS60953B2 (ja) * 1977-12-30 1985-01-11 富士通株式会社 半導体集積回路装置
US4475119A (en) * 1981-04-14 1984-10-02 Fairchild Camera & Instrument Corporation Integrated circuit power transmission array
JPS57205893A (en) * 1981-06-10 1982-12-17 Toshiba Corp Signal propagating device
JPH077825B2 (ja) * 1981-08-13 1995-01-30 富士通株式会社 ゲートアレイの製造方法
DE3313441A1 (de) * 1983-04-13 1984-10-18 Siemens AG, 1000 Berlin und 8000 München Halbleiterspeicher
US4694403A (en) * 1983-08-25 1987-09-15 Nec Corporation Equalized capacitance wiring method for LSI circuits
US4688072A (en) * 1984-06-29 1987-08-18 Hughes Aircraft Company Hierarchical configurable gate array
JPH0614536B2 (ja) * 1985-09-17 1994-02-23 株式会社東芝 バイポ−ラ集積回路
US5185283A (en) * 1987-10-22 1993-02-09 Matsushita Electronics Corporation Method of making master slice type integrated circuit device
JP2874097B2 (ja) * 1989-10-24 1999-03-24 富士通株式会社 半導体メモリ装置
US5287304A (en) * 1990-12-31 1994-02-15 Texas Instruments Incorporated Memory cell circuit and array
US5384730A (en) * 1991-05-31 1995-01-24 Thunderbird Technologies, Inc. Coincident activation of pass transistors in a random access memory
FR2690598B1 (fr) * 1992-04-24 1994-06-03 Sextant Avionique Ordonnancement de troncons de lignes d'un reseau, notamment pour le calcul de diaphonies entre lignes d'un reseau electrique.
CA2141860A1 (fr) * 1992-09-03 1994-03-17 Albert W. Vinal Activation en coincidence des transitors de chute dans une memoire vive

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL294168A (fr) * 1963-06-17
US3312871A (en) * 1964-12-23 1967-04-04 Ibm Interconnection arrangement for integrated circuits
US3447137A (en) * 1965-05-13 1969-05-27 Bunker Ramo Digital memory apparatus
US3365707A (en) * 1967-06-23 1968-01-23 Rca Corp Lsi array and standard cells
US3518635A (en) * 1967-08-22 1970-06-30 Bunker Ramo Digital memory apparatus

Also Published As

Publication number Publication date
FR2083417B1 (fr) 1974-02-15
US3638202A (en) 1972-01-25
SE359185B (fr) 1973-08-20
DE2113306A1 (de) 1971-10-14
DE2113306B2 (de) 1975-11-06
NL7103417A (fr) 1971-09-21
FR2083417A1 (fr) 1971-12-17
GB1322990A (en) 1973-07-11
JPS5116113B1 (fr) 1976-05-21

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