AU9775198A - Design rule checking system and method - Google Patents

Design rule checking system and method

Info

Publication number
AU9775198A
AU9775198A AU97751/98A AU9775198A AU9775198A AU 9775198 A AU9775198 A AU 9775198A AU 97751/98 A AU97751/98 A AU 97751/98A AU 9775198 A AU9775198 A AU 9775198A AU 9775198 A AU9775198 A AU 9775198A
Authority
AU
Australia
Prior art keywords
design rule
checking system
rule checking
design
rule
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU97751/98A
Other languages
English (en)
Inventor
Fang-Cheng Chang
Yagyensh C. Pati
Yao-Ting Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Numerical Technologies Inc
Original Assignee
Numerical Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/931,921 external-priority patent/US5858580A/en
Priority claimed from US09/130,996 external-priority patent/US6757645B2/en
Priority claimed from US09/154,397 external-priority patent/US6453452B1/en
Priority claimed from US09/153,783 external-priority patent/US6470489B1/en
Application filed by Numerical Technologies Inc filed Critical Numerical Technologies Inc
Publication of AU9775198A publication Critical patent/AU9775198A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70058—Mask illumination systems
    • G03F7/70091—Illumination settings, i.e. intensity distribution in the pupil plane or angular distribution in the field plane; On-axis or off-axis settings, e.g. annular, dipole or quadrupole settings; Partial coherence control, i.e. sigma or numerical aperture [NA]
    • G03F7/70116—Off-axis setting using a programmable means, e.g. liquid crystal display [LCD], digital micromirror device [DMD] or pupil facets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AU97751/98A 1997-09-17 1998-09-17 Design rule checking system and method Abandoned AU9775198A (en)

Applications Claiming Priority (13)

Application Number Priority Date Filing Date Title
US5930697P 1997-09-17 1997-09-17
US60059306 1997-09-17
US08931921 1997-09-17
US08/931,921 US5858580A (en) 1997-09-17 1997-09-17 Phase shifting circuit manufacture method and apparatus
US6954997P 1997-12-12 1997-12-12
US60069549 1997-12-12
US09130996 1998-08-07
US09/130,996 US6757645B2 (en) 1997-09-17 1998-08-07 Visual inspection and verification system
US09/154,397 US6453452B1 (en) 1997-12-12 1998-09-16 Method and apparatus for data hierarchy maintenance in a system for mask description
US09/153,783 US6470489B1 (en) 1997-09-17 1998-09-16 Design rule checking system and method
US09153783 1998-09-16
US09154397 1998-09-16
PCT/US1998/019510 WO1999014638A1 (en) 1997-09-17 1998-09-17 Design rule checking system and method

Publications (1)

Publication Number Publication Date
AU9775198A true AU9775198A (en) 1999-04-05

Family

ID=27556793

Family Applications (3)

Application Number Title Priority Date Filing Date
AU93960/98A Abandoned AU9396098A (en) 1997-09-17 1998-09-17 Method and apparatus for data hierarchy maintenance in a system for mask description
AU97751/98A Abandoned AU9775198A (en) 1997-09-17 1998-09-17 Design rule checking system and method
AU93961/98A Abandoned AU9396198A (en) 1997-09-17 1998-09-17 Data hierarchy layout correction and verification method and apparatus

Family Applications Before (1)

Application Number Title Priority Date Filing Date
AU93960/98A Abandoned AU9396098A (en) 1997-09-17 1998-09-17 Method and apparatus for data hierarchy maintenance in a system for mask description

Family Applications After (1)

Application Number Title Priority Date Filing Date
AU93961/98A Abandoned AU9396198A (en) 1997-09-17 1998-09-17 Data hierarchy layout correction and verification method and apparatus

Country Status (5)

Country Link
EP (2) EP1023639A4 (ja)
JP (2) JP2003526110A (ja)
KR (2) KR20010024117A (ja)
AU (3) AU9396098A (ja)
WO (1) WO1999014638A1 (ja)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6453452B1 (en) 1997-12-12 2002-09-17 Numerical Technologies, Inc. Method and apparatus for data hierarchy maintenance in a system for mask description
US7412676B2 (en) 2000-06-13 2008-08-12 Nicolas B Cobb Integrated OPC verification tool
WO2001097096A1 (en) 2000-06-13 2001-12-20 Mentor Graphics Corporation Integrated verification and manufacturability tool
US6425113B1 (en) 2000-06-13 2002-07-23 Leigh C. Anderson Integrated verification and manufacturability tool
US6978436B2 (en) 2000-07-05 2005-12-20 Synopsys, Inc. Design data format and hierarchy management for phase processing
US6430737B1 (en) 2000-07-10 2002-08-06 Mentor Graphics Corp. Convergence technique for model-based optical and process correction
JP2002122977A (ja) * 2000-10-17 2002-04-26 Sony Corp フォトマスクの作成法、フォトマスク、並びに露光方法
KR100649969B1 (ko) * 2000-12-26 2006-11-27 주식회사 하이닉스반도체 마스크 제작방법
US6395438B1 (en) 2001-01-08 2002-05-28 International Business Machines Corporation Method of etch bias proximity correction
US6505327B2 (en) 2001-04-13 2003-01-07 Numerical Technologies, Inc. Generating an instance-based representation of a design hierarchy
JP3572053B2 (ja) * 2001-05-31 2004-09-29 株式会社東芝 露光マスクの製造方法、マスク基板情報生成方法、半導体装置の製造方法およびサーバー
US6560766B2 (en) 2001-07-26 2003-05-06 Numerical Technologies, Inc. Method and apparatus for analyzing a layout using an instance-based representation
US6721928B2 (en) 2001-07-26 2004-04-13 Numerical Technologies, Inc. Verification utilizing instance-based hierarchy management
US6738958B2 (en) 2001-09-10 2004-05-18 Numerical Technologies, Inc. Modifying a hierarchical representation of a circuit to process composite gates
US6735752B2 (en) 2001-09-10 2004-05-11 Numerical Technologies, Inc. Modifying a hierarchical representation of a circuit to process features created by interactions between cells
US6880135B2 (en) 2001-11-07 2005-04-12 Synopsys, Inc. Method of incorporating lens aberration information into various process flows
US7085698B2 (en) 2001-12-18 2006-08-01 Synopsys, Inc. Method for providing flexible and dynamic reporting capability using simulation tools
US7159197B2 (en) 2001-12-31 2007-01-02 Synopsys, Inc. Shape-based geometry engine to perform smoothing and other layout beautification operations
JP4138318B2 (ja) * 2002-01-08 2008-08-27 株式会社ルネサステクノロジ リソグラフィプロセスマージン評価装置、リソグラフィプロセスマージン評価方法およびリソグラフィプロセスマージン評価プログラム
US7293249B2 (en) 2002-01-31 2007-11-06 Juan Andres Torres Robles Contrast based resolution enhancement for photolithographic processing
US7386433B2 (en) 2002-03-15 2008-06-10 Synopsys, Inc. Using a suggested solution to speed up a process for simulating and correcting an integrated circuit layout
US6944844B2 (en) 2002-04-03 2005-09-13 Synopsys, Inc. System and method to determine impact of line end shortening
US6931613B2 (en) 2002-06-24 2005-08-16 Thomas H. Kauth Hierarchical feature extraction for electrical interaction calculations
US6687895B2 (en) 2002-07-03 2004-02-03 Numerical Technologies Inc. Method and apparatus for reducing optical proximity correction output file size
US7069534B2 (en) 2003-12-17 2006-06-27 Sahouria Emile Y Mask creation with hierarchy management using cover cells
US7861207B2 (en) 2004-02-25 2010-12-28 Mentor Graphics Corporation Fragmentation point and simulation site adjustment for resolution enhancement techniques
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
WO2005111874A2 (en) * 2004-05-07 2005-11-24 Mentor Graphics Corporation Integrated circuit layout design methodology with process variation bands
US7240305B2 (en) 2004-06-02 2007-07-03 Lippincott George P OPC conflict identification and edge priority system
JP4266189B2 (ja) 2004-07-09 2009-05-20 株式会社東芝 半導体集積回路パターンの検証方法、フォトマスクの作成方法、半導体集積回路装置の製造方法、及び半導体集積回路パターンの検証方法を実現するためのプログラム
JP4904034B2 (ja) * 2004-09-14 2012-03-28 ケーエルエー−テンカー コーポレイション レチクル・レイアウト・データを評価するための方法、システム及び搬送媒体
US7617473B2 (en) * 2005-01-21 2009-11-10 International Business Machines Corporation Differential alternating phase shift mask optimization
US7506285B2 (en) 2006-02-17 2009-03-17 Mohamed Al-Imam Multi-dimensional analysis for predicting RET model accuracy
US7739650B2 (en) 2007-02-09 2010-06-15 Juan Andres Torres Robles Pre-bias optical proximity correction
CN101720474A (zh) 2007-05-23 2010-06-02 Nxp股份有限公司 工艺窗发觉检测以及掩模层处光刻印刷问题的校正
US7805699B2 (en) 2007-10-11 2010-09-28 Mentor Graphics Corporation Shape-based photolithographic model calibration
JP5100405B2 (ja) 2008-01-16 2012-12-19 株式会社東芝 データベースの作成方法およびデータベース装置
US7975244B2 (en) 2008-01-24 2011-07-05 International Business Machines Corporation Methodology and system for determining numerical errors in pixel-based imaging simulation in designing lithographic masks
US10008422B2 (en) * 2015-08-17 2018-06-26 Qoniac Gmbh Method for assessing the usability of an exposed and developed semiconductor wafer

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0608657A1 (en) * 1993-01-29 1994-08-03 International Business Machines Corporation Apparatus and method for preparing shape data for proximity correction
GB2291219B (en) * 1994-07-05 1998-07-01 Nec Corp Photo-mask fabrication and use
JPH08297692A (ja) * 1994-09-16 1996-11-12 Mitsubishi Electric Corp 光近接補正装置及び方法並びにパタン形成方法
US5682323A (en) * 1995-03-06 1997-10-28 Lsi Logic Corporation System and method for performing optical proximity correction on macrocell libraries
JP3409493B2 (ja) 1995-03-13 2003-05-26 ソニー株式会社 マスクパターンの補正方法および補正装置
US5553273A (en) * 1995-04-17 1996-09-03 International Business Machines Corporation Vertex minimization in a smart optical proximity correction system
JP2917879B2 (ja) * 1995-10-31 1999-07-12 日本電気株式会社 フォトマスク及びその製造方法
US5705301A (en) * 1996-02-27 1998-01-06 Lsi Logic Corporation Performing optical proximity correction with the aid of design rule checkers
US5801954A (en) * 1996-04-24 1998-09-01 Micron Technology, Inc. Process for designing and checking a mask layout
US5707765A (en) * 1996-05-28 1998-01-13 Microunity Systems Engineering, Inc. Photolithography mask using serifs and method thereof
DE19818440C2 (de) * 1998-04-24 2002-10-24 Pdf Solutions Gmbh Verfahren zur Erzeugung von Daten für die Herstellung einer durch Entwurfsdaten definierten Struktur

Also Published As

Publication number Publication date
EP1023639A4 (en) 2009-04-29
KR20010024113A (ko) 2001-03-26
EP1023641A4 (en) 2009-04-22
EP1023641A1 (en) 2000-08-02
JP4624550B2 (ja) 2011-02-02
AU9396098A (en) 1999-04-05
AU9396198A (en) 1999-04-05
JP2003523545A (ja) 2003-08-05
EP1023639A1 (en) 2000-08-02
KR20010024117A (ko) 2001-03-26
JP2003526110A (ja) 2003-09-02
WO1999014638A1 (en) 1999-03-25

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase