AU681220B2 - A fault tolerant queue system - Google Patents

A fault tolerant queue system Download PDF

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Publication number
AU681220B2
AU681220B2 AU12067/95A AU1206795A AU681220B2 AU 681220 B2 AU681220 B2 AU 681220B2 AU 12067/95 A AU12067/95 A AU 12067/95A AU 1206795 A AU1206795 A AU 1206795A AU 681220 B2 AU681220 B2 AU 681220B2
Authority
AU
Australia
Prior art keywords
pointers
pointer
buffer memory
blocked
list
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU12067/95A
Other languages
English (en)
Other versions
AU1206795A (en
Inventor
Tord Lennart Haulin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of AU1206795A publication Critical patent/AU1206795A/en
Application granted granted Critical
Publication of AU681220B2 publication Critical patent/AU681220B2/en
Assigned to TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) reassignment TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) Request to Amend Deed and Register Assignors: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/74Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Retry When Errors Occur (AREA)
  • Hardware Redundancy (AREA)
  • Plural Heterocyclic Compounds (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Indole Compounds (AREA)
AU12067/95A 1993-11-26 1994-11-23 A fault tolerant queue system Ceased AU681220B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9303932A SE502576C2 (sv) 1993-11-26 1993-11-26 Feltolerant kösystem
SE9303932 1993-11-26
PCT/SE1994/001119 WO1995014970A2 (en) 1993-11-26 1994-11-23 A fault tolerant queue system

Related Child Applications (1)

Application Number Title Priority Date Filing Date
AU26188/97A Division AU693056B2 (en) 1993-11-26 1997-06-20 A faulty tolerant queue system

Publications (2)

Publication Number Publication Date
AU1206795A AU1206795A (en) 1995-06-13
AU681220B2 true AU681220B2 (en) 1997-08-21

Family

ID=20391901

Family Applications (2)

Application Number Title Priority Date Filing Date
AU12067/95A Ceased AU681220B2 (en) 1993-11-26 1994-11-23 A fault tolerant queue system
AU26188/97A Ceased AU693056B2 (en) 1993-11-26 1997-06-20 A faulty tolerant queue system

Family Applications After (1)

Application Number Title Priority Date Filing Date
AU26188/97A Ceased AU693056B2 (en) 1993-11-26 1997-06-20 A faulty tolerant queue system

Country Status (17)

Country Link
US (2) US5602988A (enExample)
EP (1) EP0730764B1 (enExample)
JP (1) JPH09506452A (enExample)
KR (1) KR100301719B1 (enExample)
CN (1) CN1045675C (enExample)
AU (2) AU681220B2 (enExample)
BR (1) BR9408131A (enExample)
CA (1) CA2176471A1 (enExample)
DE (1) DE69427129T2 (enExample)
DK (1) DK0730764T3 (enExample)
ES (1) ES2155882T3 (enExample)
FI (1) FI962202A0 (enExample)
GR (1) GR3035795T3 (enExample)
NO (1) NO962120L (enExample)
SE (1) SE502576C2 (enExample)
TW (1) TW278157B (enExample)
WO (1) WO1995014970A2 (enExample)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19742378A1 (de) * 1997-09-25 1999-04-22 Siemens Ag Ringspeicher für eine TDMA-Datenübertragungsstation und entsprechende Datenübertragungsstation
US6778490B1 (en) 1998-05-20 2004-08-17 Nortel Networks Limited Method and apparatus for a fault tolerant router architecture
US6256756B1 (en) * 1998-12-04 2001-07-03 Hewlett-Packard Company Embedded memory bank system
US6363506B1 (en) * 1999-04-13 2002-03-26 Agere Systems Guardian Corp. Method for self-testing integrated circuits
US6606326B1 (en) 1999-07-02 2003-08-12 International Business Machines Corporation Packet switch employing dynamic transfer of data packet from central shared queue path to cross-point switching matrix path
US6510531B1 (en) * 1999-09-23 2003-01-21 Lucent Technologies Inc. Methods and systems for testing parallel queues
US6985455B1 (en) * 2000-03-03 2006-01-10 Hughes Electronics Corporation Method and system for providing satellite bandwidth on demand using multi-level queuing
US6584584B1 (en) * 2000-04-10 2003-06-24 Opentv, Inc. Method and apparatus for detecting errors in a First-In-First-Out buffer
US20020110094A1 (en) * 2001-02-13 2002-08-15 Reddy Naveen S. Spot beam hopping packet scheduler system
US7480239B1 (en) 2001-11-27 2009-01-20 Cisco Technology, Inc. Method and apparatus for true priority based connection establishment within a PNNI ATM network
US7161950B2 (en) * 2001-12-10 2007-01-09 Intel Corporation Systematic memory location selection in Ethernet switches
DE10162046A1 (de) * 2001-12-17 2003-06-26 Thomson Brandt Gmbh Wiedergabegerät mit einem Zwischenspeicher zum Verringern der mittleren Zugriffszeit auf einen Informationsträger
US6781898B2 (en) * 2002-10-30 2004-08-24 Broadcom Corporation Self-repairing built-in self test for linked list memories
US20050071730A1 (en) * 2003-09-30 2005-03-31 Lattice Semiconductor Corporation Continuous self-verify of configuration memory in programmable logic devices
US7532574B1 (en) 2003-10-02 2009-05-12 Cisco Technology, Inc. Method and apparatus for improved priority based connection establishment within a PNNI ATM network
US7296129B2 (en) 2004-07-30 2007-11-13 International Business Machines Corporation System, method and storage medium for providing a serialized memory interface with a bus repeater
CN101031971A (zh) * 2004-08-02 2007-09-05 皇家飞利浦电子股份有限公司 数据存储和重放设备
US7331010B2 (en) 2004-10-29 2008-02-12 International Business Machines Corporation System, method and storage medium for providing fault detection and correction in a memory subsystem
US7512762B2 (en) 2004-10-29 2009-03-31 International Business Machines Corporation System, method and storage medium for a memory subsystem with positional read data latency
US7305574B2 (en) * 2004-10-29 2007-12-04 International Business Machines Corporation System, method and storage medium for bus calibration in a memory subsystem
US7257750B1 (en) 2005-01-13 2007-08-14 Lattice Semiconductor Corporation Self-verification of configuration memory in programmable logic devices
US7802148B2 (en) * 2005-02-23 2010-09-21 Broadcom Corporation Self-correcting memory system
US7478259B2 (en) 2005-10-31 2009-01-13 International Business Machines Corporation System, method and storage medium for deriving clocks in a memory system
US7685392B2 (en) 2005-11-28 2010-03-23 International Business Machines Corporation Providing indeterminate read data latency in a memory system
US8656409B2 (en) * 2005-12-29 2014-02-18 Intel Corporation High performance queue implementations in multiprocessor systems
US7596744B1 (en) 2006-02-24 2009-09-29 Lattice Semiconductor Corporation Auto recovery from volatile soft error upsets (SEUs)
US7562260B2 (en) * 2006-04-04 2009-07-14 International Business Machines Corporation Method and system for performing recovery of a single-threaded queue
US7640386B2 (en) 2006-05-24 2009-12-29 International Business Machines Corporation Systems and methods for providing memory modules with multiple hub devices
US7669086B2 (en) 2006-08-02 2010-02-23 International Business Machines Corporation Systems and methods for providing collision detection in a memory system
US7539842B2 (en) * 2006-08-15 2009-05-26 International Business Machines Corporation Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables
US7870459B2 (en) 2006-10-23 2011-01-11 International Business Machines Corporation High density high reliability memory module with power gating and a fault tolerant address and command bus
US7721140B2 (en) * 2007-01-02 2010-05-18 International Business Machines Corporation Systems and methods for improving serviceability of a memory system
US8065574B1 (en) 2007-06-08 2011-11-22 Lattice Semiconductor Corporation Soft error detection logic testing systems and methods
CN101794242B (zh) * 2010-01-29 2012-07-18 西安交通大学 服务于操作系统核心层的容错计算机系统数据比较方法
US10866837B2 (en) * 2018-07-30 2020-12-15 Lendingclub Corporation Distributed job framework and task queue
CN119011623B (zh) * 2024-07-19 2025-10-03 南方电网电力科技股份有限公司 一种基于缓冲区的智能电表数据调度方法及装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4049956A (en) * 1975-10-08 1977-09-20 Cselt - Centro Studi E Laboratori Telecomunicazioni S.P.A. Method of and means for in-line testing of a memory operating in time-division mode
US4933932A (en) * 1987-12-24 1990-06-12 Etat Francais represente par le Ministre des Postes et Telecommunications et de l'Espace (Centre National d'Etudes des Telecommunications) Buffer queue write pointer control circuit notably for self-channelling packet time-division switching system
US5016248A (en) * 1988-10-27 1991-05-14 Kabushiki Kaisha Toshiba Buffer memory device for packet data and method of controlling the device

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3681757A (en) * 1970-06-10 1972-08-01 Cogar Corp System for utilizing data storage chips which contain operating and non-operating storage cells
US3814922A (en) * 1972-12-01 1974-06-04 Honeywell Inf Systems Availability and diagnostic apparatus for memory modules
US3863227A (en) * 1973-09-17 1975-01-28 Gte Automatic Electric Lab Inc Method and arrangement for testing a core memory
US3982111A (en) * 1975-08-04 1976-09-21 Bell Telephone Laboratories, Incorporated Memory diagnostic arrangement
US4575792A (en) * 1982-03-31 1986-03-11 Honeywell Information Systems Inc. Shared interface apparatus for testing the memory sections of a cache unit
US4479214A (en) * 1982-06-16 1984-10-23 International Business Machines Corporation System for updating error map of fault tolerant memory
US4535455A (en) * 1983-03-11 1985-08-13 At&T Bell Laboratories Correction and monitoring of transient errors in a memory system
US4672583A (en) * 1983-06-15 1987-06-09 Nec Corporation Dynamic random access memory device provided with test circuit for internal refresh circuit
US4841434A (en) * 1984-05-11 1989-06-20 Raytheon Company Control sequencer with dual microprogram counters for microdiagnostics
JPS62250593A (ja) * 1986-04-23 1987-10-31 Hitachi Ltd ダイナミツク型ram
US4809276A (en) * 1987-02-27 1989-02-28 Hutton/Prc Technology Partners 1 Memory failure detection apparatus
US5014266A (en) * 1988-12-28 1991-05-07 At&T Bell Laboratories Circuit switching system for interconnecting logical links between packet switching networks
US4953157A (en) * 1989-04-19 1990-08-28 American Telephone And Telegraph Company Programmable data packet buffer prioritization arrangement
JPH0387000A (ja) * 1989-08-30 1991-04-11 Mitsubishi Electric Corp 半導体記憶装置
US5200959A (en) * 1989-10-17 1993-04-06 Sundisk Corporation Device and method for defect handling in semi-conductor memory
US5155844A (en) * 1990-02-14 1992-10-13 International Business Machines Corporation Background memory test during system start up
US5357521A (en) * 1990-02-14 1994-10-18 International Business Machines Corporation Address sensitive memory testing
EP0459001B1 (de) * 1990-05-31 1996-01-24 Siemens Aktiengesellschaft Integrierter Halbleiterspeicher
US5276833A (en) * 1990-07-02 1994-01-04 Chips And Technologies, Inc. Data cache management system with test mode using index registers and CAS disable and posted write disable
JPH04271445A (ja) * 1990-08-02 1992-09-28 Internatl Business Mach Corp <Ibm> メモリ・テスト装置
US5177745A (en) * 1990-09-26 1993-01-05 Intel Corporation Memory device with a test mode
JPH04178580A (ja) * 1990-11-14 1992-06-25 Ando Electric Co Ltd 半導体メモリの故障自己診断装置
US5299202A (en) * 1990-12-07 1994-03-29 Trw Inc. Method and apparatus for configuration and testing of large fault-tolerant memories
EP0522224B1 (en) * 1991-07-10 1998-10-21 International Business Machines Corporation High speed buffer management
US5311520A (en) * 1991-08-29 1994-05-10 At&T Bell Laboratories Method and apparatus for programmable memory control with error regulation and test functions
KR950000305Y1 (ko) * 1991-12-23 1995-01-16 금성일렉트론 주식회사 메모리 장치의 테스트 모드회로
US5452418A (en) * 1992-04-24 1995-09-19 Digital Equipment Corporation Method of using stream buffer to perform operation under normal operation mode and selectively switching to test mode to check data integrity during system operation
US5291482A (en) * 1992-07-24 1994-03-01 At&T Bell Laboratories High bandwidth packet switch
US5388238A (en) * 1992-07-24 1995-02-07 At&T Corp. System and method for monitoring the validity of circulating pointers in a FIFO memory
SE516073C2 (sv) * 1993-02-15 2001-11-12 Ericsson Telefon Ab L M Sätt för hantering av redundanta väljarplan i paketväljare och paketväljare för utförande av sättet
US5396619A (en) * 1993-07-26 1995-03-07 International Business Machines Corporation System and method for testing and remapping base memory for memory diagnostics
US5461588A (en) * 1994-11-15 1995-10-24 Digital Equipment Corporation Memory testing with preservation of in-use data

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4049956A (en) * 1975-10-08 1977-09-20 Cselt - Centro Studi E Laboratori Telecomunicazioni S.P.A. Method of and means for in-line testing of a memory operating in time-division mode
US4933932A (en) * 1987-12-24 1990-06-12 Etat Francais represente par le Ministre des Postes et Telecommunications et de l'Espace (Centre National d'Etudes des Telecommunications) Buffer queue write pointer control circuit notably for self-channelling packet time-division switching system
US5016248A (en) * 1988-10-27 1991-05-14 Kabushiki Kaisha Toshiba Buffer memory device for packet data and method of controlling the device

Also Published As

Publication number Publication date
CN1045675C (zh) 1999-10-13
AU2618897A (en) 1997-09-04
DE69427129T2 (de) 2001-08-02
WO1995014970A2 (en) 1995-06-01
NO962120D0 (no) 1996-05-24
SE502576C2 (sv) 1995-11-13
EP0730764A1 (en) 1996-09-11
FI962202A7 (fi) 1996-05-24
US5602988A (en) 1997-02-11
AU1206795A (en) 1995-06-13
AU693056B2 (en) 1998-06-18
JPH09506452A (ja) 1997-06-24
FI962202A0 (fi) 1996-05-24
KR100301719B1 (ko) 2001-10-22
US6088817A (en) 2000-07-11
EP0730764B1 (en) 2001-04-18
SE9303932L (sv) 1995-05-27
BR9408131A (pt) 1997-08-05
DK0730764T3 (da) 2001-07-09
CN1136354A (zh) 1996-11-20
GR3035795T3 (en) 2001-07-31
SE9303932D0 (sv) 1993-11-26
NO962120L (no) 1996-05-24
ES2155882T3 (es) 2001-06-01
CA2176471A1 (en) 1995-06-01
TW278157B (enExample) 1996-06-11
DE69427129D1 (de) 2001-05-23
WO1995014970A3 (en) 1995-07-27
KR960706126A (ko) 1996-11-08

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