AU2016335548A1 - Multi-lane N-factorial encoded and other multi-wire communication systems - Google Patents

Multi-lane N-factorial encoded and other multi-wire communication systems Download PDF

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Publication number
AU2016335548A1
AU2016335548A1 AU2016335548A AU2016335548A AU2016335548A1 AU 2016335548 A1 AU2016335548 A1 AU 2016335548A1 AU 2016335548 A AU2016335548 A AU 2016335548A AU 2016335548 A AU2016335548 A AU 2016335548A AU 2016335548 A1 AU2016335548 A1 AU 2016335548A1
Authority
AU
Australia
Prior art keywords
symbols
sequence
clock signal
clock
lane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2016335548A
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English (en)
Inventor
Shoichiro Sengoku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/875,592 external-priority patent/US9735948B2/en
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of AU2016335548A1 publication Critical patent/AU2016335548A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
AU2016335548A 2015-10-05 2016-09-09 Multi-lane N-factorial encoded and other multi-wire communication systems Abandoned AU2016335548A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/875,592 US9735948B2 (en) 2013-10-03 2015-10-05 Multi-lane N-factorial (N!) and other multi-wire communication systems
US14/875,592 2015-10-05
PCT/US2016/051131 WO2017062132A1 (en) 2015-10-05 2016-09-09 Multi-lane n-factorial encoded and other multi-wire communication systems

Publications (1)

Publication Number Publication Date
AU2016335548A1 true AU2016335548A1 (en) 2018-04-12

Family

ID=56997556

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2016335548A Abandoned AU2016335548A1 (en) 2015-10-05 2016-09-09 Multi-lane N-factorial encoded and other multi-wire communication systems

Country Status (8)

Country Link
EP (1) EP3360278A1 (enExample)
JP (1) JP2018534847A (enExample)
KR (1) KR102520096B1 (enExample)
CN (1) CN108141346A (enExample)
AU (1) AU2016335548A1 (enExample)
BR (1) BR112018006874A2 (enExample)
TW (1) TW201714443A (enExample)
WO (1) WO2017062132A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI778603B (zh) 2020-04-30 2022-09-21 台灣積體電路製造股份有限公司 積體電路及其製造方法
US11437998B2 (en) 2020-04-30 2022-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including back side conductive lines for clock signals

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05227173A (ja) * 1992-02-10 1993-09-03 Oki Electric Ind Co Ltd 多重処理方式
US9711041B2 (en) * 2012-03-16 2017-07-18 Qualcomm Incorporated N-phase polarity data transfer
US9030976B2 (en) * 2008-03-27 2015-05-12 Silicon Image, Inc. Bi-directional digital interface for video and audio (DIVA)
JP2013110554A (ja) * 2011-11-21 2013-06-06 Panasonic Corp 送信装置、受信装置及びシリアル伝送システム
US8996740B2 (en) * 2012-06-29 2015-03-31 Qualcomm Incorporated N-phase polarity output pin mode multiplexer
EP2914033B1 (en) * 2012-10-26 2020-01-15 Hitachi Kokusai Electric Inc. Multichannel wireless communication system, base station, and method for using channel
US9337997B2 (en) * 2013-03-07 2016-05-10 Qualcomm Incorporated Transcoding method for multi-wire signaling that embeds clock information in transition of signal state
US9582457B2 (en) * 2013-06-12 2017-02-28 Qualcomm Incorporated Camera control interface extension bus
US9755818B2 (en) * 2013-10-03 2017-09-05 Qualcomm Incorporated Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes
US20150220472A1 (en) * 2014-02-05 2015-08-06 Qualcomm Incorporated Increasing throughput on multi-wire and multi-lane interfaces
KR101688377B1 (ko) * 2014-03-06 2017-01-02 퀄컴 인코포레이티드 다중 와이어 데이터 신호들에 대한 클록 복원 회로

Also Published As

Publication number Publication date
EP3360278A1 (en) 2018-08-15
TW201714443A (zh) 2017-04-16
KR102520096B1 (ko) 2023-04-07
KR20180066065A (ko) 2018-06-18
CN108141346A (zh) 2018-06-08
JP2018534847A (ja) 2018-11-22
WO2017062132A1 (en) 2017-04-13
BR112018006874A2 (pt) 2018-10-16

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Legal Events

Date Code Title Description
MK1 Application lapsed section 142(2)(a) - no request for examination in relevant period