BR112018006874A2 - sistemas de comunicação codificados de n fatores de várias pistas e outros sistemas de comunicação de vários fios - Google Patents

sistemas de comunicação codificados de n fatores de várias pistas e outros sistemas de comunicação de vários fios

Info

Publication number
BR112018006874A2
BR112018006874A2 BR112018006874A BR112018006874A BR112018006874A2 BR 112018006874 A2 BR112018006874 A2 BR 112018006874A2 BR 112018006874 A BR112018006874 A BR 112018006874A BR 112018006874 A BR112018006874 A BR 112018006874A BR 112018006874 A2 BR112018006874 A2 BR 112018006874A2
Authority
BR
Brazil
Prior art keywords
communication systems
clock signal
receiving apparatus
wire
factor
Prior art date
Application number
BR112018006874A
Other languages
English (en)
Portuguese (pt)
Inventor
Sengoku Shoichiro
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/875,592 external-priority patent/US9735948B2/en
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018006874A2 publication Critical patent/BR112018006874A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
BR112018006874A 2015-10-05 2016-09-09 sistemas de comunicação codificados de n fatores de várias pistas e outros sistemas de comunicação de vários fios BR112018006874A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/875,592 US9735948B2 (en) 2013-10-03 2015-10-05 Multi-lane N-factorial (N!) and other multi-wire communication systems
PCT/US2016/051131 WO2017062132A1 (en) 2015-10-05 2016-09-09 Multi-lane n-factorial encoded and other multi-wire communication systems

Publications (1)

Publication Number Publication Date
BR112018006874A2 true BR112018006874A2 (pt) 2018-10-16

Family

ID=56997556

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018006874A BR112018006874A2 (pt) 2015-10-05 2016-09-09 sistemas de comunicação codificados de n fatores de várias pistas e outros sistemas de comunicação de vários fios

Country Status (8)

Country Link
EP (1) EP3360278A1 (enExample)
JP (1) JP2018534847A (enExample)
KR (1) KR102520096B1 (enExample)
CN (1) CN108141346A (enExample)
AU (1) AU2016335548A1 (enExample)
BR (1) BR112018006874A2 (enExample)
TW (1) TW201714443A (enExample)
WO (1) WO2017062132A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113192950B (zh) 2020-04-30 2025-04-18 台湾积体电路制造股份有限公司 集成电路及其制造方法
US11437998B2 (en) 2020-04-30 2022-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including back side conductive lines for clock signals

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05227173A (ja) * 1992-02-10 1993-09-03 Oki Electric Ind Co Ltd 多重処理方式
US9711041B2 (en) * 2012-03-16 2017-07-18 Qualcomm Incorporated N-phase polarity data transfer
US9030976B2 (en) * 2008-03-27 2015-05-12 Silicon Image, Inc. Bi-directional digital interface for video and audio (DIVA)
JP2013110554A (ja) * 2011-11-21 2013-06-06 Panasonic Corp 送信装置、受信装置及びシリアル伝送システム
US8996740B2 (en) * 2012-06-29 2015-03-31 Qualcomm Incorporated N-phase polarity output pin mode multiplexer
WO2014065002A1 (ja) * 2012-10-26 2014-05-01 株式会社日立国際電気 マルチチャネル無線通信システム、基地局、チャネル利用方法
US9363071B2 (en) * 2013-03-07 2016-06-07 Qualcomm Incorporated Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches
US9639499B2 (en) * 2013-06-12 2017-05-02 Qualcomm Incorporated Camera control interface extension bus
US9755818B2 (en) * 2013-10-03 2017-09-05 Qualcomm Incorporated Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes
US20150220472A1 (en) * 2014-02-05 2015-08-06 Qualcomm Incorporated Increasing throughput on multi-wire and multi-lane interfaces
EP3114792B1 (en) * 2014-03-06 2021-06-09 Qualcomm Incorporated Clock recovery circuit for multiple wire data signals

Also Published As

Publication number Publication date
TW201714443A (zh) 2017-04-16
WO2017062132A1 (en) 2017-04-13
CN108141346A (zh) 2018-06-08
KR20180066065A (ko) 2018-06-18
AU2016335548A1 (en) 2018-04-12
EP3360278A1 (en) 2018-08-15
JP2018534847A (ja) 2018-11-22
KR102520096B1 (ko) 2023-04-07

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Legal Events

Date Code Title Description
B11Y Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette]