AU2003234496A1 - Method and apparatus for soft defect detection in a memory - Google Patents

Method and apparatus for soft defect detection in a memory

Info

Publication number
AU2003234496A1
AU2003234496A1 AU2003234496A AU2003234496A AU2003234496A1 AU 2003234496 A1 AU2003234496 A1 AU 2003234496A1 AU 2003234496 A AU2003234496 A AU 2003234496A AU 2003234496 A AU2003234496 A AU 2003234496A AU 2003234496 A1 AU2003234496 A1 AU 2003234496A1
Authority
AU
Australia
Prior art keywords
memory
defect detection
soft defect
soft
detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003234496A
Other languages
English (en)
Inventor
Lawrence N. Herr
Thomas W. Liston
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AU2003234496A1 publication Critical patent/AU2003234496A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1202—Word line control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1204—Bit line control
AU2003234496A 2002-06-17 2003-05-07 Method and apparatus for soft defect detection in a memory Abandoned AU2003234496A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/173,229 2002-06-17
US10/173,229 US6590818B1 (en) 2002-06-17 2002-06-17 Method and apparatus for soft defect detection in a memory
PCT/US2003/014107 WO2003107355A1 (en) 2002-06-17 2003-05-07 Method and apparatus for soft defect detection in a memory

Publications (1)

Publication Number Publication Date
AU2003234496A1 true AU2003234496A1 (en) 2003-12-31

Family

ID=22631081

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003234496A Abandoned AU2003234496A1 (en) 2002-06-17 2003-05-07 Method and apparatus for soft defect detection in a memory

Country Status (7)

Country Link
US (1) US6590818B1 (enExample)
JP (1) JP2005530299A (enExample)
KR (1) KR20050008829A (enExample)
CN (1) CN100501876C (enExample)
AU (1) AU2003234496A1 (enExample)
TW (1) TWI301272B (enExample)
WO (1) WO2003107355A1 (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19951048C2 (de) * 1999-10-22 2002-11-21 Infineon Technologies Ag Verfahren zur Identifizierung einer integrierten Schaltung
US6834017B2 (en) * 2002-10-03 2004-12-21 Hewlett-Packard Development Company, L.P. Error detection system for an information storage device
KR100585090B1 (ko) * 2003-06-04 2006-05-30 삼성전자주식회사 스태틱 메모리셀 소프트 결함 검출수단을 구비하는 반도체집적회로 및 이의 소프트 결함 검출방법
EP2057636A2 (en) 2006-08-22 2009-05-13 Nxp B.V. Method for testing a static random access memory
US7872930B2 (en) * 2008-05-15 2011-01-18 Qualcomm, Incorporated Testing a memory device having field effect transistors subject to threshold voltage shifts caused by bias temperature instability
US8797813B2 (en) 2011-05-17 2014-08-05 Maxlinear, Inc. Method and apparatus for memory power and/or area reduction
KR101300590B1 (ko) * 2011-10-18 2013-08-27 넷솔 주식회사 메모리 장치 및 이의 테스트 방법
US9236144B2 (en) * 2014-03-12 2016-01-12 Intel IP Corporation For-test apparatuses and techniques
KR20170029914A (ko) * 2015-09-08 2017-03-16 에스케이하이닉스 주식회사 메모리 장치 및 이의 동작 방법
US10891992B1 (en) 2017-02-16 2021-01-12 Synopsys, Inc. Bit-line repeater insertion architecture
US10867665B1 (en) * 2017-02-16 2020-12-15 Synopsys, Inc. Reset before write architecture and method
US10431265B2 (en) * 2017-03-23 2019-10-01 Silicon Storage Technology, Inc. Address fault detection in a flash memory system
CN111161785A (zh) * 2019-12-31 2020-05-15 展讯通信（上海）有限公司 静态随机存储器及其故障检测电路
DE102021106756A1 (de) * 2020-05-29 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren zum testen einer speicherschaltung und speicherschaltung
CN112349341B (zh) * 2020-11-09 2024-05-28 深圳佰维存储科技股份有限公司 Lpddr测试方法、装置、可读存储介质及电子设备
US11594275B2 (en) 2021-07-12 2023-02-28 Changxin Memory Technologies, Inc. Method for detecting leakage position in memory and device for detecting leakage position in memory
CN114187956B (zh) * 2022-01-14 2023-09-05 长鑫存储技术有限公司 存储器预充电时长边界的测试方法、装置、设备及存储介质
CN114582411B (zh) * 2022-03-01 2024-12-06 长鑫存储技术有限公司 存储器检测方法、电路、装置、设备及存储介质

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719418A (en) 1985-02-19 1988-01-12 International Business Machines Corporation Defect leakage screen system
US5034923A (en) 1987-09-10 1991-07-23 Motorola, Inc. Static RAM with soft defect detection
US5428574A (en) 1988-12-05 1995-06-27 Motorola, Inc. Static RAM with test features
US5255230A (en) * 1991-12-31 1993-10-19 Intel Corporation Method and apparatus for testing the continuity of static random access memory cells
CA2212089C (en) * 1997-07-31 2006-10-24 Mosaid Technologies Incorporated Bist memory test system
US6163862A (en) * 1997-12-01 2000-12-19 International Business Machines Corporation On-chip test circuit for evaluating an on-chip signal using an external test signal
JP2000322900A (ja) 1999-05-12 2000-11-24 Mitsubishi Electric Corp 半導体記録装置
TW473728B (en) * 1999-07-22 2002-01-21 Koninkl Philips Electronics Nv A method for testing a memory array and a memory-based device so testable with a fault response signalizing mode for when finding predetermined correspondence between fault patterns signalizing one such fault pattern only in the form of a compressed resp
US6108257A (en) * 1999-09-30 2000-08-22 Philips Electronics North America Corporation Zero power SRAM precharge
WO2001086660A1 (en) * 2000-05-09 2001-11-15 Koninklijke Philips Electronics N.V. Integrated circuit containing sram memory and method of testing same
CA2345845C (en) * 2001-04-30 2012-03-27 Mosaid Technologies Incorporated Bitline precharge

Also Published As

Publication number Publication date
TW200405351A (en) 2004-04-01
KR20050008829A (ko) 2005-01-21
WO2003107355A1 (en) 2003-12-24
TWI301272B (en) 2008-09-21
CN1662997A (zh) 2005-08-31
US6590818B1 (en) 2003-07-08
CN100501876C (zh) 2009-06-17
JP2005530299A (ja) 2005-10-06

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase