Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
  • G11C2029/1202—Word line control
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
  • G11C2029/1204—Bit line control

Definitions

• the present invention relates generally to memories, and more specifically, to soft defect error detection in memories.
• Soft defects generally refer to those defects which appear under certain conditions and do not appear under other conditions. For example, a soft defect may be one that only appears at a specific voltage, temperature, and time. These soft defects are therefore difficult to detect.
• One known method for detecting soft defects tests SRAM (static random access memory) cells by writing predetermined data to them and reading them after a waiting period.
• the waiting period must be relatively long in order to ensure that all abnormal memory cells are failed which results in longer testing times. Therefore, any test techniques which require long waiting periods for testing incurs higher test cost.
• the above method fails to capture all soft-defects. Therefore, a need exists for an improved soft-defect detection technique which reduces testing cost and improves testing time.
• FIG. 1 illustrates, in block diagram form, a memory in accordance with one embodiment of the present invention
• FIG. 2 illustrates, in schematic form, a shorting and charging circuit of FIG. 1 in accordance with one embodiment of the present invention
• FIG. 3 illustrates, in flow diagram form, a soft defect detection method in accordance with one embodiment of the present invention.
• FIG. 4 illustrates, in schematic form, an SRAM cell in accordance with one embodiment of the present invention
• FIGs. 5-6 illustrate, in graph form, voltage waveforms corresponding to the SRAM cell of FIG. 4, in accordance with various embodiments of the present invention.
• bus is used to refer to a plurality of signals or conductors which may be used to transfer one or more various types of information, such as data, addresses, control, or status.
• the conductors as discussed herein may be illustrated or described in reference to being a single conductor, a plurality of conductors, unidirectional conductors, or bidirectional conductors. However, different embodiments may vary the implementation of the conductors. For example, separate unidirectional conductors may be used rather than bidirectional conductors and vice versa.
• plurality of conductors may be replaced with a single conductor that transfers multiple signals serially or in a time multiplexed manner. Likewise, single conductors carrying multiple signals may be separated out into various different conductors carrying subsets of these signals. Therefore, many options exist for transferring signals.
• assert and “negate” (or “deassert”) are used when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero.
• Brackets is used to indicate the conductors of a bus or the bit locations of a value.
• bus 60 [0-7]” or “conductors [0-7] of bus 60” indicates the eight lower order conductors of bus 60
• "address bits [0-7]” or “ADDRESS [0-7]” indicates the eight lower order bits of an address value.
• the symbol “$” preceding a number indicates that the number is represented in its hexadecimal or base sixteen form.
• the symbol “%” preceding a number indicates that the number is represented in its binary or base two form.
• FIG. 1 illustrates, in block diagram form, a memory 10 in accordance with one embodiment of the present invention.
• memory 10 (also referred to as memory array 10) is an SRAM; however, in alternate embodiments, the soft defect detection (SDD) techniques discussed herein can apply to any type of memory.
• memory 10 may refer to either an embedded memory or a stand alone memory.
• Memory 10 includes M+l word lines WL 0 - WL M and N+l pairs of bit lines BL 0 , BL 0 Bar - BL N , BL N Bar.
• memory 10 is an M+l by N+l memory having M+l rows and N+l columns. At the intersection of each bit line pair and word line is a memory cell (or bit cell) like memory cell 12. Memory 10 may therefore include any number of rows and columns.
• the word lines WL 0 - WL M are selected by word line decoder 14 coupled to each of the word lines.
• word line decoder may receive address bits which selects one of the word lines.
• the bit line pairs are coupled to bit line decoders and sense amplifiers 16.
• Bit line decoders and sense amplifiers 16 may also include bit line precharge circuitry which may statically or dynamically precharge the bit line pairs to predetermined voltages. For example, each bit line may be precharged to Vdd and each complementary bit line (bit line bar) may also be precharged to Vdd.
• bit line bar each complementary bit line (bit line bar) may also be precharged to Vdd.
• a sense amplifier coupled to the corresponding bit line pairs, is used to sense the values within the selected bit cells.
• a sense amplifier may be coupled to each of the bit line pairs of memory 10.
• a group of bit line pairs may share a single sense amplifier through the use of switching circuitry, such as a multiplexer.
• Memory 10 also includes circuitry for operating in an SDD mode.
• Memory 10 also includes SDD bit line conditioning circuits 20, 21, and 22 between each pair of bit lines. That is, SDD bit line conditioning circuit 20 is coupled between BL 0 and BL 0 Bar, SDD bit line conditioning circuit 21 is coupled between BLi and BLiBar, and SDD bit line conditioning circuit 22 is coupled between BL N and BL N Bar.
• Memory 10 includes soft defect test control 18 which receives an SDD enable signal, SDD En, and provides control signals to word line decoder 14 via conductors 15, to bit line decoders and sense amplifiers 16 via conductors 17, and to each SDD bit line conditioning circuit (including condition circuits 20, 21, and 22) via conductors 19.
• SDD En is asserted.
• the bit line precharge circuits 16 are disabled.
• the multiplexers, if any, within bit line decoders and sense amplifiers 16 may or may not be disabled.
• the functionality of word line decoder 14 is controlled by soft defect test control 18.
• SDD mode includes a charging phase, a shorting phase, and a word line activation phase.
• the charging phase and shorting phase may be referred to, in combination, as a bit line conditioning phase.
• soft defect test control 18 provides a SDD_charge signal to conditioning circuits 20, 21, and 22 (via conductors 19).
• each of conditioning circuits 20, 21, and 22 couple its corresponding bit line to a first predetermined voltage and its complementary bit line to a second predetermined voltage.
• the corresponding bit line is coupled to Vss and the complementary bit line to Vdd.
• bit line may be coupled to Vdd and the complementary bit line to Vss.
• any voltages may be used as the first and second predetermined voltages.
• Vdd is greater than Vss, where, in one embodiment, Vss refers to ground, and Vdd the power supply voltage. Therefore, Vdd and Vss may also each be referred to as power supply voltages.
• each conditioning circuit 20, 21, and 22 couples its corresponding bit line to its corresponding complementary bit line in response to an SDD_short signal received from soft detect test control 18 via conductors 19 in order to average the voltage levels between the bit line and complementary bit line upon activation of the corresponding word line.
• the resulting average voltage level on the bit line and complementary bit line is Vdd/2. The resulting average voltage level allows for each transistor within the activated bit cells to be electrically conductive when the word line is activated (i.e. addressed). If each transistor is electrically conductive, then a soft defect within any of the transistors can be detected. An example will be described in reference to an SRAM 6T cell illustrated in FIG. 4.
• FIG. 2 illustrates conditioning circuit 21 in accordance with one embodiment of the present invention.
• Conditioning circuitry 21 of FIG. 2 includes a transmission gate 37 coupled between BLi and BLiBar where the transmission gate includes a PMOS transistor 36 coupled to an NMOS transistor 34. That is, a first current electrode of transistor 36 is coupled to a first current electrode of transistor 34 and to BLi at a node 31. A second current electrode of transistor 36 is coupled to a second current electrode of transistor 34 and to BLiBar at a node 35.
• a control electrode of transistor 34 is coupled to receive SDD_short from soft defect test control 18 and is also coupled to the input of an inverter 33.
• the output of inverter 33 is coupled to a control electrode of transistor 36.
• Conditioning circuit 21 also includes an NMOS transistor 30 having a first current electrode coupled to node 31, a second current electrode coupled to Vss, and a control electrode coupled to receive SDD_charge from soft defect test control 18.
• the control electrode of transistor 30 is also coupled to an input of inverter 40.
• Conditioning circuitry 21 also includes a PMOS transistor 38 having a first current electrode coupled to Vdd and a second current electrode coupled to node 35.
• the output of inverter 40 is coupled to a control electrode of transistor 38.
• transistors 30 and 38 perform the charging phase by coupling Vss to BLi and Vdd to BLiBar in response to SDD_charge being asserted. After SDD_charge is deasserted, SDD_short is asserted in order to equalize the charge between BLi and BLiBar via transistors 36 and 34. After the charge is equalized, SDD_short may be deasserted. However, in alternate embodiments SDD_short may remain asserted during the word line activation phase, which will be discussed below. Note also that a variety of different circuitries may be used to accomplish the same or similar functionality as the example of FIG. 2.
• a selected word line for example, WL 0
• soft defect test control 18 provides control signals to word line decoder 14 to activate the selected word line.
• fully functional bit cells i.e. those without any soft defects
• any defective bit cells along the activated word line which are not in their preferred state will change states. For example, if the preferred state of bit cell 12 of FIG.
• bit cell 12 (assuming bit cell 12 includes a soft defect) is a 1 and it is written with a 0 for testing (prior to activation of WL 0 ), activation of WL 0 will result in a state change (from a 0 to a 1). However, if bit cell 12 was written to a 1 for testing, activation of WLo may not result in a state change. Therefore, in some embodiments, in order to fully test bit cell 12, charging, shorting, and activation should be performed using both states 0 and 1, as will be described in more detail in reference to the flow diagram of FIG. 3. As mentioned above, during the word line activation phase, BL 0 and BL 0 Bar may or may not be still coupled together, depending on the embodiment.
• the charging, shorting, and word line activation phases may be repeated, where in the word line activation phase, a new word line is selected for activation.
• the transition among the various phases can be implemented using a state machine.
• external addresses used to cycle through the bit cells of memory 12 may be used to cycle through the various phases.
• the two least significant bits of the external addresses may be used to cycle through the 3 phases.
• each bit line and complementary bit line can be coupled to a same voltage potential. That is, during a conditioning phase, prior to the word line activation phase, each bit line and complementary bit line can be coupled to a same voltage potential rather than coupling each to a different predetermined voltage and then shorting them together. Therefore, during the conditioning phase, the bit line and complementary bit line are set to voltage potentials which result in each transistor within the activated bit cells to be electrically conductive.
• each bit cell may include transistors for storing a value as well as transistors for accessing the stored value.
• Soft defects may be detected in any of the transistors for storing the value when all the transistors for storing the value are electrically conductive during the SDD mode.
• FIG. 1 also includes an evaluator 8 coupled to receive information from bit line decoders and sense amplifiers 16 of memory 10 and analyze the results to determine if any defective bit cells exist.
• Evaluator 8 may be located on chip with memory 10 or may be an external analyzer or tester.
• evaluator 8 may be a built in self tester (BIST), functional pattern, or an external programmable tester.
• evaluator 8 may be a dedicated analyzer or a non-dedicated analyzer.
• evaluator 8 compares the values within the memory array 10 (after the conditioning and word line activation phases) with the values originally written to the memory array 10 (prior to the conditioning and word line activation phases) to determine the existence of defective bit cells. For example, a mismatch in the comparison indicates a defective bit cell.
• FIG. 3 illustrates, in flow diagram form, one embodiment of an
• SDD method The flow of FIG. 3 begins with start 40 and proceeds to block 42 where memory array 10 is written with a current test state. For example, memory array 10 can be written with all ones or all zeroes, or with any test pattern.
• Flow proceeds to block 44 where selected bit lines are conditioned (i.e. a conditioning phase). For example, as described above, in an embodiment using an SRAM cell, selected bit line pairs (each having a bit line and a complementary bit line) are conditioned in this step. In one embodiment, one bit line or bit line pair may be conditioned or a group of bit lines or bit line pairs may be conditioned (such as, for example, a group of bit line pairs along a same word line).
• conditioning the bit lines includes charging each bit line and its corresponding complementary bit line to a first and second predetermined voltage, respectively (i.e. a charging phase).
• the bit line can be charged to Vss and the complementary bit line to Vdd.
• conditioning the bit lines also includes connecting each bit line to its corresponding complementary bit line (i.e. a shorting phase). This equalizes the charges between the bit line and complementary bit line.
• a variety of different methods may be used to perform the conditioning phase.
• a predetermined word line is activated (i.e. a word line activation phase) which allows a defective bit cell, if one exists, to change states.
• Flow then proceeds to decision diamond 48 where it is determined if more word lines to activate exists. If so, flow returns to block 44 where another bit line or group of bit lines are conditioned (such as a group of bit lines along a different word line) and in block 46, the new word line is activated. Therefore, in one embodiment, the word lines are cycled through sequentially, where each time through the loop (i.e. blocks 44 and 46), all the bit lines along the current word line are conditioned.
• the next test state may correspond to writing all ones to memory array 10 such that all bit cells are fully evaluated with both a logic one and a logic zero.
• more than two test states may be used where the flow of FIG. 3 is performed more than two times.
• only one test state may be used. Once all the test states are tested (at decision diamond 52), flow finishes with end 56.
• FIG. 4 illustrates in schematic form, one example of bit cell 12 of FIG. 1.
• bit cell 12 is a 6T SRAM cell in accordance with one embodiment of the present invention.
• Bit cell 12 includes transistors 70, 74, 78, and 80, and access transistors 82 and 84.
• a first current electrode of access transistor 82 is coupled to BL 0 and a second current electrode of access transistor 82 is coupled to node 72.
• a control electrode of access transistor 82 is coupled to WL 0 .
• a first current electrode of transistor 70 and a first current electrode of transistor 74 are coupled to Vdd, and a second current electrode of transistor 70 and a control electrode of transistor 74 are coupled to node 72.
• a second current electrode of transistor 74 and a control electrode of transistor 70 are coupled to a node 76.
• a first current electrode of transistor 78 is coupled to node 72, a second current electrode of transistor 78 is coupled to Vss, and a control electrode of transistor 78 is coupled to node 76.
• a first current electrode of transistor 80 is coupled to node 76, a second current electrode of transistor 80 is coupled to Vss, and a control electrode of transistor 80 is coupled to node 72.
• a first current electrode of access transistor 84 is coupled to node 76, a second current electrode of access transistor 84 is coupled to BL 0 Bar, and a control electrode of access transistor 84 is coupled to WL 0 .
• transistors 70 and 74 are PMOS transistors and transistors 78, 80, 82, and 84 are NMOS transistors.
• the 6T SRAM cell operates as known in the art. That is, nodes 72 and 76 store a value which may be accessed (read or written) via access transistors 82 and 84 which are activated via the corresponding word line for the bit cell. Therefore, transistors 70, 74, 78, and 80 operate to store a value while transistors 82 and 84 are used for accessing the stored value. However, note that when access transistors 82 and 84 are active, they may also operate to help store the stored value. Furthermore, when access transistors 82 and 84 are active, transistors 70 and 74 may not be needed.
• the charges on BLo and BL 0 Bar are equalized (via charging and shorting phases) or set to a same voltage in order to ensure that transistors 70, 74, 78, and 80 are electrically conductive upon activation of WL 0 .
• the average voltage level is Vdd/2 which makes all transistors 70, 74, 78, and 80 electrically conductive.
• the series-connected transistors 70 and 78 and series-connected transistors 74 and 80 are conductive (where, in the illustrated example, transistors 70 and 78, as well as transistors 74 and 80, are of opposite conductivity types).
• FIG. 6 illustrates waveforms corresponding to the voltage at node 72 and the voltage at node 76. If the voltage at node 72 is originally high (corresponding to Vdd) and the voltage at node 76 is originally low (corresponding to Vss), then bit cell 12 stores a logic level one. Upon activation of WLo, indicated by arrow 91 in FIG. 6, access transistors 82 and 84 are activated and the voltage at node 76 rises because as current is conducted via transistors 84 and 80, the voltage of transistor 80 increases.
• the voltage at node 72 drops because when BL 0 is at Vdd/2, current is pulled from Vdd via transistors 70 and 82.
• the voltages at nodes 72 and 76 eventually reach a steady state value.
• the voltages at nodes 72 and 76 simply return to the original values which correspond to the same state as was stored prior to activating the word line. That is, a state change in bit cell 12 does not occur.
• the difference in voltage 90 in FIG. 6 should remain large enough to ensure robust operation. That is, if the different 90 becomes too small, then bit cell 12 may become too sensitive to process variations.
• FIG. 5 illustrates waveforms corresponding to the voltage at node 72 and the voltage at node 76, assuming bit cell 12 is defective (in the current example, transistor 70 is assumed to be defective).
• bit cell 12 stores a logic level one.
• access transistors 82 and 84 are activated. Since transistor 70 is considered to be defective (resistive or open) in the current example, the voltage at node 72 drops by a sufficiently large amount to cause bit cell 12 to become unstable and thereby change states. For example, when the voltage of node 72 drops too much, transistor 80 begins to conduct less current and transistor 74 conducts more current. This can cause transistor 78 to conduct more current which eventually destroys the stored value in bit cell 12. Also, the voltage at node 76 rises because, as stated previously, transistor 74 conducts more. As seen in FIG. 5, the defective transistor 70 results in a state change. Therefore, upon deactivation of the corresponding word line (illustrated by arrow 89 in FIG. 5), bit cell 12 stores a different state (e.g. a logic level 0).
• a different state e.g. a logic level 0
• any defect in any one or more of transistors 70, 74, 78, and 80 results in a state change of bit cell 12 due to instability within the bit cell caused by the defective transistor or transistors.
• this state change occurs upon activation of the corresponding word line, which allows for at speed testing for soft defects.
• At speed testing refers to testing at a speed that is substantially similar to the normal operating speed of memory 10. That is, a long waiting time after activation of the word line is not required since the state change (assuming a defect exists) occurs immediately in response to the word line activation. Note also that the waveforms of FIGs.
• the SDD methods described herein may be used on multiple bit cells in parallel. For example, all bit cells along a selected word line may be conditioned in parallel for subsequent word line activation. In this manner, activation of a single word line affects multiple bit cells which further reduces testing time.
• the peak (or dynamic) currents can be controlled such that the conditioning phase does not draw anymore current than is drawn during normal operation of the memory.

Landscapes

• For Increasing The Reliability Of Semiconductor Memories (AREA)
• Static Random-Access Memory (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (1)

Family

ID=22631081

Family Applications (1)

Country Status (7)

Families Citing this family (18)

Citations (3)

Family Cites Families (8)

• 2002
  • 2002-06-17 US US10/173,229 patent/US6590818B1/en not_active Expired - Fee Related
• 2003
  • 2003-05-07 AU AU2003234496A patent/AU2003234496A1/en not_active Abandoned
  • 2003-05-07 WO PCT/US2003/014107 patent/WO2003107355A1/en not_active Ceased
  • 2003-05-07 JP JP2004514085A patent/JP2005530299A/ja active Pending
  • 2003-05-07 CN CNB038140888A patent/CN100501876C/zh not_active Expired - Fee Related
  • 2003-05-07 KR KR10-2004-7020439A patent/KR20050008829A/ko not_active Ceased
  • 2003-06-16 TW TW092116262A patent/TWI301272B/zh not_active IP Right Cessation

Patent Citations (3)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events