AU2003223892A1 - Method and device for data processing - Google Patents

Method and device for data processing

Info

Publication number
AU2003223892A1
AU2003223892A1 AU2003223892A AU2003223892A AU2003223892A1 AU 2003223892 A1 AU2003223892 A1 AU 2003223892A1 AU 2003223892 A AU2003223892 A AU 2003223892A AU 2003223892 A AU2003223892 A AU 2003223892A AU 2003223892 A1 AU2003223892 A1 AU 2003223892A1
Authority
AU
Australia
Prior art keywords
data processing
data
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003223892A
Other languages
English (en)
Other versions
AU2003223892A8 (en
Inventor
Martin Vorbach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PACT XPP Technologies AG
Original Assignee
PACT XPP Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10212622A external-priority patent/DE10212622A1/de
Priority claimed from DE10226186A external-priority patent/DE10226186A1/de
Priority claimed from DE10227650A external-priority patent/DE10227650A1/de
Priority claimed from PCT/EP2002/006865 external-priority patent/WO2002103532A2/fr
Priority claimed from PCT/EP2002/010065 external-priority patent/WO2003017095A2/fr
Priority claimed from DE10238174A external-priority patent/DE10238174A1/de
Priority claimed from DE10238172A external-priority patent/DE10238172A1/de
Priority claimed from DE10238173A external-priority patent/DE10238173A1/de
Priority claimed from DE10240000A external-priority patent/DE10240000A1/de
Priority claimed from PCT/DE2002/003278 external-priority patent/WO2003023616A2/fr
Priority claimed from DE2002141812 external-priority patent/DE10241812A1/de
Priority claimed from PCT/EP2002/010479 external-priority patent/WO2003025781A2/fr
Priority claimed from PCT/EP2002/010572 external-priority patent/WO2003036507A2/fr
Priority claimed from PCT/EP2003/000624 external-priority patent/WO2003071418A2/fr
Priority claimed from PCT/DE2003/000152 external-priority patent/WO2003060747A2/fr
Priority claimed from PCT/DE2003/000489 external-priority patent/WO2003071432A2/fr
Application filed by PACT XPP Technologies AG filed Critical PACT XPP Technologies AG
Publication of AU2003223892A1 publication Critical patent/AU2003223892A1/en
Publication of AU2003223892A8 publication Critical patent/AU2003223892A8/xx
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU2003223892A 2002-03-21 2003-03-21 Method and device for data processing Abandoned AU2003223892A1 (en)

Applications Claiming Priority (55)

Application Number Priority Date Filing Date Title
DE10212621 2002-03-21
DE10212622A DE10212622A1 (de) 2002-03-21 2002-03-21 Prozessorkopplung
DE10212622.4 2002-03-21
DE10212621.6 2002-03-21
EP02009868.7 2002-05-02
EP02009868 2002-05-02
DE10219681 2002-05-02
DE10219681.8 2002-05-02
DE10226186A DE10226186A1 (de) 2002-02-15 2002-06-12 IO-Entkopplung
DE10226186.5 2002-06-12
DE10227650A DE10227650A1 (de) 2001-06-20 2002-06-20 Rekonfigurierbare Elemente
AU2002347560 2002-06-20
DE10227650.1 2002-06-20
PCT/EP2002/006865 WO2002103532A2 (fr) 2001-06-20 2002-06-20 Procede de traitement de donnees
DE10236272.6 2002-08-07
DE10236269.6 2002-08-07
DE10236271.8 2002-08-07
DE10236271 2002-08-07
DE10236272 2002-08-07
DE10236269 2002-08-07
PCT/EP2002/010065 WO2003017095A2 (fr) 2001-08-16 2002-08-16 Procede permettant la conversion de programmes destines a des architectures reconfigurables
AU2002340879 2002-08-16
DE10238173A DE10238173A1 (de) 2002-08-07 2002-08-21 Rekonfigurationsdatenladeverfahren
DE10238173.9 2002-08-21
DE10238172A DE10238172A1 (de) 2002-08-07 2002-08-21 Verfahren und Vorrichtung zur Datenverarbeitung
DE10238174.7 2002-08-21
DE10238174A DE10238174A1 (de) 2002-08-07 2002-08-21 Verfahren und Vorrichtung zur Datenverarbeitung
DE10238172.0 2002-08-21
DE10240000A DE10240000A1 (de) 2002-08-27 2002-08-27 Busssysteme und Rekonfigurationsverfahren
DE10240000.8 2002-08-27
DE10240022 2002-08-27
DE10240022.9 2002-08-27
PCT/DE2002/003278 WO2003023616A2 (fr) 2001-09-03 2002-09-03 Procede de debogage d'architectures reconfigurables
AU2002336896 2002-09-03
DE2002141812 DE10241812A1 (de) 2002-09-06 2002-09-06 Rekonfigurierbare Sequenzerstruktur
DE10241812.8 2002-09-06
EP0210464 2002-09-18
PCT/EP2002/010479 WO2003025781A2 (fr) 2001-09-19 2002-09-18 Routeur
AU2002342709 2002-09-18
AU2002338729 2002-09-18
PCT/EP2002/010572 WO2003036507A2 (fr) 2001-09-19 2002-09-19 Elements reconfigurables
AU2002357982 2002-09-19
EP02022692 2002-10-10
EP02022692.4 2002-10-10
EP02027277.9 2002-12-06
EP02027277 2002-12-06
DE10300380 2003-01-07
DE10300380.0 2003-01-07
AU2003208266 2003-01-20
AU2003214046 2003-01-20
PCT/EP2003/000624 WO2003071418A2 (fr) 2002-01-18 2003-01-20 Procede de compilation
PCT/DE2003/000152 WO2003060747A2 (fr) 2002-01-19 2003-01-20 Processeur reconfigurable
PCT/DE2003/000489 WO2003071432A2 (fr) 2002-02-18 2003-02-18 Systemes de bus et procede de reconfiguration
AU2003214003 2003-02-18
PCT/DE2003/000942 WO2003081454A2 (fr) 2002-03-21 2003-03-21 Procede et dispositif de traitement de donnees

Publications (2)

Publication Number Publication Date
AU2003223892A1 true AU2003223892A1 (en) 2003-10-08
AU2003223892A8 AU2003223892A8 (en) 2003-10-08

Family

ID=56290401

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003223892A Abandoned AU2003223892A1 (en) 2002-03-21 2003-03-21 Method and device for data processing

Country Status (4)

Country Link
US (3) US20060075211A1 (fr)
EP (1) EP1518186A2 (fr)
AU (1) AU2003223892A1 (fr)
WO (1) WO2003081454A2 (fr)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT501479B8 (de) * 2003-12-17 2007-02-15 On Demand Informationstechnolo Digitale rechnereinrichtung
WO2005073866A2 (fr) * 2004-01-21 2005-08-11 Charles Stark Draper Laboratory, Inc. Systemes et procede de calcul reconfigurable
US8966223B2 (en) * 2005-05-05 2015-02-24 Icera, Inc. Apparatus and method for configurable processing
US9081901B2 (en) * 2007-10-31 2015-07-14 Raytheon Company Means of control for reconfigurable computers
WO2009060567A1 (fr) * 2007-11-09 2009-05-14 Panasonic Corporation Dispositif de commande de transfert de données, dispositif de transfert de données, procédé de commande de transfert de données et circuit intégré semi-conducteur utilisant un circuit reconfiguré
US9003165B2 (en) * 2008-12-09 2015-04-07 Shlomo Selim Rakib Address generation unit using end point patterns to scan multi-dimensional data structures
CN106708753B (zh) 2012-03-30 2021-04-02 英特尔公司 在使用共享虚拟存储器的处理器中加速操作的装置和方法
US9471433B2 (en) 2014-03-19 2016-10-18 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets
US9471329B2 (en) 2014-03-19 2016-10-18 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets
JP2016178229A (ja) 2015-03-20 2016-10-06 株式会社東芝 再構成可能な回路
GB2536658B (en) * 2015-03-24 2017-03-22 Imagination Tech Ltd Controlling data flow between processors in a processing system
US10353709B2 (en) * 2017-09-13 2019-07-16 Nextera Video, Inc. Digital signal processing array using integrated processing elements
US10426424B2 (en) 2017-11-21 2019-10-01 General Electric Company System and method for generating and performing imaging protocol simulations
FR3086409A1 (fr) * 2018-09-26 2020-03-27 Stmicroelectronics (Grenoble 2) Sas Procede de gestion de la fourniture d'informations, en particulier des instructions, a un microprocesseur et systeme correspondant
US11803507B2 (en) 2018-10-29 2023-10-31 Secturion Systems, Inc. Data stream protocol field decoding by a systolic array
CN111124514B (zh) * 2019-12-19 2023-03-28 杭州迪普科技股份有限公司 框式设备业务板松耦合的实现方法、系统及框式设备
CN117435259B (zh) * 2023-12-20 2024-03-22 芯瞳半导体技术(山东)有限公司 Vpu的配置方法、装置、电子设备及计算机可读存储介质

Family Cites Families (143)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2067477A (en) * 1931-03-20 1937-01-12 Allis Chalmers Mfg Co Gearing
GB971191A (en) * 1962-05-28 1964-09-30 Wolf Electric Tools Ltd Improvements relating to electrically driven equipment
US3564506A (en) * 1968-01-17 1971-02-16 Ibm Instruction retry byte counter
US5459846A (en) * 1988-12-02 1995-10-17 Hyatt; Gilbert P. Computer architecture system having an imporved memory
US4498134A (en) * 1982-01-26 1985-02-05 Hughes Aircraft Company Segregator functional plane for use in a modular array processor
US4498172A (en) * 1982-07-26 1985-02-05 General Electric Company System for polynomial division self-testing of digital networks
US4566102A (en) * 1983-04-18 1986-01-21 International Business Machines Corporation Parallel-shift error reconfiguration
US4571736A (en) * 1983-10-31 1986-02-18 University Of Southwestern Louisiana Digital communication system employing differential coding and sample robbing
US4646300A (en) * 1983-11-14 1987-02-24 Tandem Computers Incorporated Communications method
US4720778A (en) * 1985-01-31 1988-01-19 Hewlett Packard Company Software debugging analyzer
US5225719A (en) * 1985-03-29 1993-07-06 Advanced Micro Devices, Inc. Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix
US4720780A (en) * 1985-09-17 1988-01-19 The Johns Hopkins University Memory-linked wavefront array processor
US4910665A (en) * 1986-09-02 1990-03-20 General Electric Company Distributed processing system including reconfigurable elements
US5367208A (en) * 1986-09-19 1994-11-22 Actel Corporation Reconfigurable programmable interconnect architecture
GB2211638A (en) * 1987-10-27 1989-07-05 Ibm Simd array processor
FR2606184B1 (fr) * 1986-10-31 1991-11-29 Thomson Csf Dispositif de calcul reconfigurable
US4811214A (en) * 1986-11-14 1989-03-07 Princeton University Multinode reconfigurable pipeline computer
US5081575A (en) * 1987-11-06 1992-01-14 Oryx Corporation Highly parallel computer architecture employing crossbar switch with selectable pipeline delay
US5055999A (en) * 1987-12-22 1991-10-08 Kendall Square Research Corporation Multiprocessor digital data processing system
US5287511A (en) * 1988-07-11 1994-02-15 Star Semiconductor Corporation Architectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tasks for a decision making microprocessor interfacing therewith
US4901268A (en) * 1988-08-19 1990-02-13 General Electric Company Multiple function data processor
US5081375A (en) * 1989-01-19 1992-01-14 National Semiconductor Corp. Method for operating a multiple page programmable logic device
GB8906145D0 (en) * 1989-03-17 1989-05-04 Algotronix Ltd Configurable cellular array
US5203005A (en) * 1989-05-02 1993-04-13 Horst Robert W Cell structure for linear array wafer scale integration architecture with capability to open boundary i/o bus without neighbor acknowledgement
CA2021192A1 (fr) * 1989-07-28 1991-01-29 Malcolm A. Mumme Processeur maille synchrone simplifie
US5489857A (en) * 1992-08-03 1996-02-06 Advanced Micro Devices, Inc. Flexible synchronous/asynchronous cell structure for a high density programmable logic device
GB8925723D0 (en) * 1989-11-14 1990-01-04 Amt Holdings Processor array system
US5099447A (en) * 1990-01-22 1992-03-24 Alliant Computer Systems Corporation Blocked matrix multiplication for computers with hierarchical memory
US5483620A (en) * 1990-05-22 1996-01-09 International Business Machines Corp. Learning machine synapse processor system apparatus
US5193202A (en) * 1990-05-29 1993-03-09 Wavetracer, Inc. Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
US5590345A (en) * 1990-11-13 1996-12-31 International Business Machines Corporation Advanced parallel array processor(APAP)
US5734921A (en) * 1990-11-13 1998-03-31 International Business Machines Corporation Advanced parallel array processor computer package
US5752067A (en) * 1990-11-13 1998-05-12 International Business Machines Corporation Fully scalable parallel processing system having asynchronous SIMD processing
CA2051029C (fr) * 1990-11-30 1996-11-05 Pradeep S. Sindhu Arbitrage de bus de transmission de paquets commutes, y compris les bus de multiprocesseurs a memoire commune
US5276836A (en) * 1991-01-10 1994-01-04 Hitachi, Ltd. Data processing device with common memory connecting mechanism
JPH04328657A (ja) * 1991-04-30 1992-11-17 Toshiba Corp キャッシュメモリ
US5260610A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic element interconnections for programmable logic array integrated circuits
FR2681791B1 (fr) * 1991-09-27 1994-05-06 Salomon Sa Dispositif d'amortissement des vibrations pour club de golf.
JP2791243B2 (ja) * 1992-03-13 1998-08-27 株式会社東芝 階層間同期化システムおよびこれを用いた大規模集積回路
US5493663A (en) * 1992-04-22 1996-02-20 International Business Machines Corporation Method and apparatus for predetermining pages for swapping from physical memory in accordance with the number of accesses
US5611049A (en) * 1992-06-03 1997-03-11 Pitts; William M. System for accessing distributed data cache channel at each network node to pass requests and data
US5386154A (en) * 1992-07-23 1995-01-31 Xilinx, Inc. Compact logic cell for field programmable gate array chip
US5581778A (en) * 1992-08-05 1996-12-03 David Sarnoff Researach Center Advanced massively parallel computer using a field of the instruction to selectively enable the profiling counter to increase its value in response to the system clock
DE69331061T2 (de) * 1992-08-10 2002-06-06 Monolithic System Tech Inc Fehlertolerantes hierarchisiertes Bussystem
US5857109A (en) * 1992-11-05 1999-01-05 Giga Operations Corporation Programmable logic device for real time video processing
US5497498A (en) * 1992-11-05 1996-03-05 Giga Operations Corporation Video processing module using a second programmable logic device which reconfigures a first programmable logic device for data transformation
US5392437A (en) * 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5386518A (en) * 1993-02-12 1995-01-31 Hughes Aircraft Company Reconfigurable computer interface and method
US5596742A (en) * 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
AU6774894A (en) * 1993-04-26 1994-11-21 Comdisco Systems, Inc. Method for scheduling synchronous data flow graphs
US5896551A (en) * 1994-04-15 1999-04-20 Micron Technology, Inc. Initializing and reprogramming circuitry for state independent memory array burst operations control
US5600845A (en) * 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5603005A (en) * 1994-12-27 1997-02-11 Unisys Corporation Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed
US5493239A (en) * 1995-01-31 1996-02-20 Motorola, Inc. Circuit and method of configuring a field programmable gate array
US5862403A (en) * 1995-02-17 1999-01-19 Kabushiki Kaisha Toshiba Continuous data server apparatus and data transfer scheme enabling multiple simultaneous data accesses
JP3313007B2 (ja) * 1995-04-14 2002-08-12 三菱電機株式会社 マイクロコンピュータ
US5933642A (en) * 1995-04-17 1999-08-03 Ricoh Corporation Compiling system and method for reconfigurable computing
JP3948494B2 (ja) * 1995-04-28 2007-07-25 ザイリンクス，インコーポレイテッド プログラム可能論理装置によってアクセス可能な分散レジスタを有するマイクロプロセサ
GB9508931D0 (en) * 1995-05-02 1995-06-21 Xilinx Inc Programmable switch for FPGA input/output signals
US5600597A (en) * 1995-05-02 1997-02-04 Xilinx, Inc. Register protection structure for FPGA
JPH08328941A (ja) * 1995-05-31 1996-12-13 Nec Corp メモリアクセス制御回路
JP3677315B2 (ja) * 1995-06-01 2005-07-27 シャープ株式会社 データ駆動型情報処理装置
US5889982A (en) * 1995-07-01 1999-03-30 Intel Corporation Method and apparatus for generating event handler vectors based on both operating mode and event type
US5784313A (en) * 1995-08-18 1998-07-21 Xilinx, Inc. Programmable logic device including configuration data or user data memory slices
US5943242A (en) * 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
US5732209A (en) * 1995-11-29 1998-03-24 Exponential Technology, Inc. Self-testing multi-processor die with internal compare points
US7266725B2 (en) * 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
KR0165515B1 (ko) * 1996-02-17 1999-01-15 김광호 그래픽 데이터의 선입선출기 및 선입선출 방법
US6020758A (en) * 1996-03-11 2000-02-01 Altera Corporation Partially reconfigurable programmable logic device
US6173434B1 (en) * 1996-04-22 2001-01-09 Brigham Young University Dynamically-configurable digital processor using method for relocating logic array modules
US5894565A (en) * 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
US5887165A (en) * 1996-06-21 1999-03-23 Mirage Technologies, Inc. Dynamically reconfigurable hardware system for real-time control of processes
US6023742A (en) * 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
US6023564A (en) * 1996-07-19 2000-02-08 Xilinx, Inc. Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions
US5859544A (en) * 1996-09-05 1999-01-12 Altera Corporation Dynamic configurable elements for programmable logic devices
US6178494B1 (en) * 1996-09-23 2001-01-23 Virtual Computer Corporation Modular, hybrid processor and method for producing a modular, hybrid processor
US6167486A (en) * 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
US5860119A (en) * 1996-11-25 1999-01-12 Vlsi Technology, Inc. Data-packet fifo buffer system with end-of-packet flags
DE19654593A1 (de) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit
US6338106B1 (en) * 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
DE19654595A1 (de) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE19704044A1 (de) * 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Verfahren zur automatischen Adressgenerierung von Bausteinen innerhalb Clustern aus einer Vielzahl dieser Bausteine
US5865239A (en) * 1997-02-05 1999-02-02 Micropump, Inc. Method for making herringbone gears
DE19704728A1 (de) * 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
US5884075A (en) * 1997-03-10 1999-03-16 Compaq Computer Corporation Conflict resolution using self-contained virtual devices
US5857097A (en) * 1997-03-10 1999-01-05 Digital Equipment Corporation Method for identifying reasons for dynamic stall cycles during the execution of a program
US6195674B1 (en) * 1997-04-30 2001-02-27 Canon Kabushiki Kaisha Fast DCT apparatus
US6035371A (en) * 1997-05-28 2000-03-07 3Com Corporation Method and apparatus for addressing a static random access memory device based on signals for addressing a dynamic memory access device
US6011407A (en) * 1997-06-13 2000-01-04 Xilinx, Inc. Field programmable gate array with dedicated computer bus interface and method for configuring both
US5966534A (en) * 1997-06-27 1999-10-12 Cooke; Laurence H. Method for compiling high level programming languages into an integrated processor with reconfigurable logic
US6020760A (en) * 1997-07-16 2000-02-01 Altera Corporation I/O buffer circuit with pin multiplexing
US6026478A (en) * 1997-08-01 2000-02-15 Micron Technology, Inc. Split embedded DRAM processor
US6170051B1 (en) * 1997-08-01 2001-01-02 Micron Technology, Inc. Apparatus and method for program level parallelism in a VLIW processor
US6038656A (en) * 1997-09-12 2000-03-14 California Institute Of Technology Pipelined completion for asynchronous communication
SG82587A1 (en) * 1997-10-21 2001-08-21 Sony Corp Recording apparatus, recording method, playback apparatus, playback method, recording/playback apparatus, recording/playback method, presentation medium and recording medium
JPH11147335A (ja) * 1997-11-18 1999-06-02 Fuji Xerox Co Ltd 描画処理装置
JP4197755B2 (ja) * 1997-11-19 2008-12-17 富士通株式会社 信号伝送システム、該信号伝送システムのレシーバ回路、および、該信号伝送システムが適用される半導体記憶装置
DE69841256D1 (de) * 1997-12-17 2009-12-10 Panasonic Corp Befehlsmaskierung um Befehlsströme einem Prozessor zuzuleiten
DE69827589T2 (de) * 1997-12-17 2005-11-03 Elixent Ltd. Konfigurierbare Verarbeitungsanordnung und Verfahren zur Benutzung dieser Anordnung, um eine Zentraleinheit aufzubauen
DE19861088A1 (de) * 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
US6172520B1 (en) * 1997-12-30 2001-01-09 Xilinx, Inc. FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
US6105106A (en) * 1997-12-31 2000-08-15 Micron Technology, Inc. Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times
US6034538A (en) * 1998-01-21 2000-03-07 Lucent Technologies Inc. Virtual logic system for reconfigurable hardware
US6198304B1 (en) * 1998-02-23 2001-03-06 Xilinx, Inc. Programmable logic device
DE19807872A1 (de) * 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Verfahren zur Verwaltung von Konfigurationsdaten in Datenflußprozessoren sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstruktur (FPGAs, DPGAs, o. dgl.
US6173419B1 (en) * 1998-05-14 2001-01-09 Advanced Technology Materials, Inc. Field programmable gate array (FPGA) emulator for debugging software
JP3123977B2 (ja) * 1998-06-04 2001-01-15 日本電気株式会社 プログラマブル機能ブロック
US6202182B1 (en) * 1998-06-30 2001-03-13 Lucent Technologies Inc. Method and apparatus for testing field programmable gate arrays
US6272594B1 (en) * 1998-07-31 2001-08-07 Hewlett-Packard Company Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes
US6137307A (en) * 1998-08-04 2000-10-24 Xilinx, Inc. Structure and method for loading wide frames of data from a narrow input bus
JP3551353B2 (ja) * 1998-10-02 2004-08-04 株式会社日立製作所 データ再配置方法
US6044030A (en) * 1998-12-21 2000-03-28 Philips Electronics North America Corporation FIFO unit with single pointer
US6694434B1 (en) * 1998-12-23 2004-02-17 Entrust Technologies Limited Method and apparatus for controlling program execution and program distribution
US6381715B1 (en) * 1998-12-31 2002-04-30 Unisys Corporation System and method for performing parallel initialization and testing of multiple memory banks and interfaces in a shared memory module
US7003660B2 (en) * 2000-06-13 2006-02-21 Pact Xpp Technologies Ag Pipeline configuration unit protocols and communication
US6191614B1 (en) * 1999-04-05 2001-02-20 Xilinx, Inc. FPGA configuration circuit including bus-based CRC register
US7007096B1 (en) * 1999-05-12 2006-02-28 Microsoft Corporation Efficient splitting and mixing of streaming-data frames for processing through multiple processing modules
US6211697B1 (en) * 1999-05-25 2001-04-03 Actel Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure
US6347346B1 (en) * 1999-06-30 2002-02-12 Chameleon Systems, Inc. Local memory unit system with global access for use on reconfigurable chips
US6341318B1 (en) * 1999-08-10 2002-01-22 Chameleon Systems, Inc. DMA data streaming
US6204687B1 (en) * 1999-08-13 2001-03-20 Xilinx, Inc. Method and structure for configuring FPGAS
US6507947B1 (en) * 1999-08-20 2003-01-14 Hewlett-Packard Company Programmatic synthesis of processor element arrays
US6349346B1 (en) * 1999-09-23 2002-02-19 Chameleon Systems, Inc. Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit
US6625654B1 (en) * 1999-12-28 2003-09-23 Intel Corporation Thread signaling in multi-threaded network processor
US6519674B1 (en) * 2000-02-18 2003-02-11 Chameleon Systems, Inc. Configuration bits layout
US6845445B2 (en) * 2000-05-12 2005-01-18 Pts Corporation Methods and apparatus for power control in a scalable array of processor elements
US6362650B1 (en) * 2000-05-18 2002-03-26 Xilinx, Inc. Method and apparatus for incorporating a multiplier into an FPGA
US6711407B1 (en) * 2000-07-13 2004-03-23 Motorola, Inc. Array of processors architecture for a space-based network router
EP1182559B1 (fr) * 2000-08-21 2009-01-21 Texas Instruments Incorporated Microprocesseur
US6518787B1 (en) * 2000-09-21 2003-02-11 Triscend Corporation Input/output architecture for efficient configuration of programmable input/output cells
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US6525678B1 (en) * 2000-10-06 2003-02-25 Altera Corporation Configuring a programmable logic device
US6636919B1 (en) * 2000-10-16 2003-10-21 Motorola, Inc. Method for host protection during hot swap in a bridged, pipelined network
US6493250B2 (en) * 2000-12-28 2002-12-10 Intel Corporation Multi-tier point-to-point buffered memory interface
US20020108021A1 (en) * 2001-02-08 2002-08-08 Syed Moinul I. High performance cache and method for operating same
US6847370B2 (en) * 2001-02-20 2005-01-25 3D Labs, Inc., Ltd. Planar byte memory organization with linear access
US6976239B1 (en) * 2001-06-12 2005-12-13 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
JP3580785B2 (ja) * 2001-06-29 2004-10-27 株式会社半導体理工学研究センター ルックアップテーブル、ルックアップテーブルを備えるプログラマブル論理回路装置、および、ルックアップテーブルの構成方法
US20030055861A1 (en) * 2001-09-18 2003-03-20 Lai Gary N. Multipler unit in reconfigurable chip
US20030052711A1 (en) * 2001-09-19 2003-03-20 Taylor Bradley L. Despreader/correlator unit for use in reconfigurable chip
US6757784B2 (en) * 2001-09-28 2004-06-29 Intel Corporation Hiding refresh of memory and refresh-hidden memory
US7000161B1 (en) * 2001-10-15 2006-02-14 Altera Corporation Reconfigurable programmable logic system with configuration recovery mode
US7873811B1 (en) * 2003-03-10 2011-01-18 The United States Of America As Represented By The United States Department Of Energy Polymorphous computing fabric

Also Published As

Publication number Publication date
US20100174868A1 (en) 2010-07-08
WO2003081454A2 (fr) 2003-10-02
WO2003081454A8 (fr) 2004-02-12
WO2003081454A3 (fr) 2005-01-27
EP1518186A2 (fr) 2005-03-30
AU2003223892A8 (en) 2003-10-08
US20150074352A1 (en) 2015-03-12
US20060075211A1 (en) 2006-04-06

Similar Documents

Publication Publication Date Title
AU2003286131A1 (en) Method and device for processing data
AU2003249919A1 (en) Method and device for processing multimedia data
AU2003211584A1 (en) Data processing apparatus and method thereof
AU2003242104A1 (en) Processing device and processing method
AU2003235587A1 (en) Processing device and processing method
AU2003240157A1 (en) Method and device for data input
AU2003294319A1 (en) Apparatus and method for matrix data processing
AU2003289189A1 (en) Device and method for laser processing
AU2003274737A1 (en) Information processing method and information processing apparatus
AU2003289291A1 (en) Image processing device and image processing method
AU2003265847A1 (en) Apparatus and methods for locating data
AU2003237197A1 (en) Method and apparatus for transporting data
GB0228665D0 (en) Data processing apparatus and method
AU2003264521A1 (en) Information processing device and information processing method
EP1603336A4 (fr) Dispositif et procede de traitement de donnees
AU2003241503A1 (en) Methods and apparatus for radar data processing
AU2003242422A1 (en) Substrate processing device and substrate processing method
AU2003290787A1 (en) Device and method for editing processed data input
EP1643768A4 (fr) Dispositif et procede de traitement de donnees
AU2003223892A1 (en) Method and device for data processing
AU2003268645A1 (en) Data processing method, its program, and its device
AU2003272931A1 (en) System development method and data processing system
AU2003290325A1 (en) Data retrieval method and apparatus
AU2003246171A1 (en) Processing device and processing method
AU2003289409A1 (en) Processing method and device

Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase