AU2001292762A1 - Integrating metal with ultra low-k dielectrics - Google Patents

Integrating metal with ultra low-k dielectrics

Info

Publication number
AU2001292762A1
AU2001292762A1 AU2001292762A AU9276201A AU2001292762A1 AU 2001292762 A1 AU2001292762 A1 AU 2001292762A1 AU 2001292762 A AU2001292762 A AU 2001292762A AU 9276201 A AU9276201 A AU 9276201A AU 2001292762 A1 AU2001292762 A1 AU 2001292762A1
Authority
AU
Australia
Prior art keywords
dielectrics
ultra low
integrating metal
integrating
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001292762A
Other languages
English (en)
Inventor
Hui Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ACM Research Inc
Original Assignee
ACM Research Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ACM Research Inc filed Critical ACM Research Inc
Publication of AU2001292762A1 publication Critical patent/AU2001292762A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/02—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Weting (AREA)
AU2001292762A 2000-09-18 2001-09-18 Integrating metal with ultra low-k dielectrics Abandoned AU2001292762A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US23358700P 2000-09-18 2000-09-18
US60233587 2000-09-18
PCT/US2001/029173 WO2002023616A1 (en) 2000-09-18 2001-09-18 Integrating metal with ultra low-k dielectrics

Publications (1)

Publication Number Publication Date
AU2001292762A1 true AU2001292762A1 (en) 2002-03-26

Family

ID=22877855

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001292762A Abandoned AU2001292762A1 (en) 2000-09-18 2001-09-18 Integrating metal with ultra low-k dielectrics

Country Status (10)

Country Link
US (1) US7119008B2 (zh)
EP (1) EP1325516A4 (zh)
JP (1) JP2004509467A (zh)
KR (1) KR101031682B1 (zh)
CN (2) CN101577247B (zh)
AU (1) AU2001292762A1 (zh)
CA (1) CA2421799A1 (zh)
IL (1) IL154869A0 (zh)
TW (1) TW518707B (zh)
WO (1) WO2002023616A1 (zh)

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US6299741B1 (en) 1999-11-29 2001-10-09 Applied Materials, Inc. Advanced electrolytic polish (AEP) assisted metal wafer planarization method and apparatus
US6537144B1 (en) 2000-02-17 2003-03-25 Applied Materials, Inc. Method and apparatus for enhanced CMP using metals having reductive properties
US6848970B2 (en) 2002-09-16 2005-02-01 Applied Materials, Inc. Process control in electrochemically assisted planarization
US7066800B2 (en) 2000-02-17 2006-06-27 Applied Materials Inc. Conductive polishing article for electrochemical mechanical polishing
US6811680B2 (en) 2001-03-14 2004-11-02 Applied Materials Inc. Planarization of substrates using electrochemical mechanical polishing
US6951599B2 (en) 2002-01-22 2005-10-04 Applied Materials, Inc. Electropolishing of metallic interconnects
WO2003088352A1 (en) * 2002-04-09 2003-10-23 Rensselaer Polytechnic Institute Electrochemical planarization of metal feature surfaces
TWI300971B (en) 2002-04-12 2008-09-11 Hitachi Ltd Semiconductor device
JP2006128722A (ja) * 2002-04-12 2006-05-18 Renesas Technology Corp 半導体装置
US6984301B2 (en) * 2002-07-18 2006-01-10 Micron Technology, Inc. Methods of forming capacitor constructions
US7842169B2 (en) 2003-03-04 2010-11-30 Applied Materials, Inc. Method and apparatus for local polishing control
US7070207B2 (en) * 2003-04-22 2006-07-04 Ibiden Co., Ltd. Substrate for mounting IC chip, multilayerd printed circuit board, and device for optical communication
US7244673B2 (en) * 2003-11-12 2007-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integration film scheme for copper / low-k interconnect
US7382012B2 (en) * 2006-02-24 2008-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing parasitic capacitance of MIM capacitor in integrated circuits by reducing effective dielectric constant of dielectric layer
JP5194393B2 (ja) * 2006-06-23 2013-05-08 東京エレクトロン株式会社 半導体装置の製造方法
US8268722B2 (en) * 2009-06-03 2012-09-18 Novellus Systems, Inc. Interfacial capping layers for interconnects
CN102332427A (zh) * 2011-10-13 2012-01-25 上海华力微电子有限公司 第一层铜互连的制作方法
CN103692293B (zh) * 2012-09-27 2018-01-16 盛美半导体设备（上海）有限公司 无应力抛光装置及抛光方法
US10181443B2 (en) * 2013-02-04 2019-01-15 Taiwan Semiconductor Manufacturing Company Limited Support structure for barrier layer of semiconductor device
US9633896B1 (en) 2015-10-09 2017-04-25 Lam Research Corporation Methods for formation of low-k aluminum-containing etch stop films
US9859156B2 (en) * 2015-12-30 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure with sidewall dielectric protection layer
WO2018062470A1 (ja) 2016-09-30 2018-04-05 富士フイルム株式会社 半導体チップの製造方法、キット

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5340370A (en) * 1993-11-03 1994-08-23 Intel Corporation Slurries for chemical mechanical polishing
US5880018A (en) * 1996-10-07 1999-03-09 Motorola Inc. Method for manufacturing a low dielectric constant inter-level integrated circuit structure
JP3116897B2 (ja) 1998-03-18 2000-12-11 日本電気株式会社 微細配線形成方法
US6284050B1 (en) 1998-05-18 2001-09-04 Novellus Systems, Inc. UV exposure for improving properties and adhesion of dielectric polymer films formed by chemical vapor deposition
US6395152B1 (en) * 1998-07-09 2002-05-28 Acm Research, Inc. Methods and apparatus for electropolishing metal interconnections on semiconductor devices
MXPA00005871A (es) * 1998-10-14 2002-08-06 Faraday Technology Inc ELECTRODEPOSICION DE METALES EN RECESOS PEQUEnOS USANDO CAMPOS ELECTRICOS MODULADOS.
US6259160B1 (en) * 1999-04-21 2001-07-10 Advanced Micro Devices, Inc. Apparatus and method of encapsulated copper (Cu) Interconnect formation
US6136707A (en) * 1999-10-02 2000-10-24 Cohen; Uri Seed layers for interconnects and methods for fabricating such seed layers
US6252290B1 (en) * 1999-10-25 2001-06-26 Chartered Semiconductor Manufacturing Ltd. Method to form, and structure of, a dual damascene interconnect device
US6736952B2 (en) * 2001-02-12 2004-05-18 Speedfam-Ipec Corporation Method and apparatus for electrochemical planarization of a workpiece
US6790336B2 (en) * 2002-06-19 2004-09-14 Intel Corporation Method of fabricating damascene structures in mechanically weak interlayer dielectrics

Also Published As

Publication number Publication date
WO2002023616A8 (en) 2002-07-11
IL154869A0 (en) 2003-10-31
KR101031682B1 (ko) 2011-04-29
JP2004509467A (ja) 2004-03-25
TW518707B (en) 2003-01-21
US7119008B2 (en) 2006-10-10
WO2002023616A1 (en) 2002-03-21
US20040266130A1 (en) 2004-12-30
EP1325516A4 (en) 2007-06-06
CN101577247A (zh) 2009-11-11
CA2421799A1 (en) 2002-03-21
CN101577247B (zh) 2011-12-14
KR20030040468A (ko) 2003-05-22
CN1732561A (zh) 2006-02-08
EP1325516A2 (en) 2003-07-09

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