AU2001289169A1 - Semiconductor memory having dual port cell supporting hidden refresh - Google Patents

Semiconductor memory having dual port cell supporting hidden refresh

Info

Publication number
AU2001289169A1
AU2001289169A1 AU2001289169A AU8916901A AU2001289169A1 AU 2001289169 A1 AU2001289169 A1 AU 2001289169A1 AU 2001289169 A AU2001289169 A AU 2001289169A AU 8916901 A AU8916901 A AU 8916901A AU 2001289169 A1 AU2001289169 A1 AU 2001289169A1
Authority
AU
Australia
Prior art keywords
semiconductor memory
dual port
cell supporting
hidden refresh
port cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001289169A
Other languages
English (en)
Inventor
Chuck Dennison
Brent Keeth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of AU2001289169A1 publication Critical patent/AU2001289169A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/907—Folded bit line dram configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
AU2001289169A 2000-08-30 2001-08-29 Semiconductor memory having dual port cell supporting hidden refresh Abandoned AU2001289169A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US65054600A 2000-08-30 2000-08-30
US09/650,546 2000-08-30
PCT/US2001/041940 WO2002019341A2 (en) 2000-08-30 2001-08-29 Semiconductor memory having dual port cell supporting hidden refresh

Publications (1)

Publication Number Publication Date
AU2001289169A1 true AU2001289169A1 (en) 2002-03-13

Family

ID=24609357

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001289169A Abandoned AU2001289169A1 (en) 2000-08-30 2001-08-29 Semiconductor memory having dual port cell supporting hidden refresh

Country Status (7)

Country Link
US (2) US6438016B1 (ko)
EP (2) EP1323168A2 (ko)
JP (1) JP2004508654A (ko)
KR (1) KR100702355B1 (ko)
CN (1) CN100559504C (ko)
AU (1) AU2001289169A1 (ko)
WO (1) WO2002019341A2 (ko)

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US6862654B1 (en) * 2000-08-17 2005-03-01 Micron Technology, Inc. Method and system for using dynamic random access memory as cache memory
US6779076B1 (en) 2000-10-05 2004-08-17 Micron Technology, Inc. Method and system for using dynamic random access memory as cache memory
CA2340985A1 (en) * 2001-03-14 2002-09-14 Atmos Corporation Interleaved wordline architecture
KR100389130B1 (ko) * 2001-04-25 2003-06-25 삼성전자주식회사 2비트 동작의 2트랜지스터를 구비한 불휘발성 메모리소자
TWI252406B (en) * 2001-11-06 2006-04-01 Mediatek Inc Memory access interface and access method for a microcontroller system
JP2003257178A (ja) * 2002-03-06 2003-09-12 Matsushita Electric Ind Co Ltd 半導体メモリ装置
JP2003317469A (ja) * 2002-04-19 2003-11-07 Mitsubishi Electric Corp マルチポートメモリ回路
US7617356B2 (en) * 2002-12-31 2009-11-10 Intel Corporation Refresh port for a dynamic memory
US6724645B1 (en) * 2003-01-30 2004-04-20 Agilent Technologies, Inc. Method and apparatus for shortening read operations in destructive read memories
US20050289293A1 (en) * 2004-06-28 2005-12-29 Parris Michael C Dual-port DRAM cell with simultaneous access
US20060190678A1 (en) * 2005-02-22 2006-08-24 Butler Douglas B Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag
US7506100B2 (en) * 2005-02-23 2009-03-17 United Memories, Inc. Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks
US7372092B2 (en) * 2005-05-05 2008-05-13 Micron Technology, Inc. Memory cell, device, and system
US7488664B2 (en) * 2005-08-10 2009-02-10 Micron Technology, Inc. Capacitor structure for two-transistor DRAM memory cell and method of forming same
US7313047B2 (en) * 2006-02-23 2007-12-25 Hynix Semiconductor Inc. Dynamic semiconductor memory with improved refresh mechanism
CN107180649B (zh) * 2016-03-11 2021-01-15 联华电子股份有限公司 半导体存储器元件及操作半导体存储器元件的方法
WO2018044510A1 (en) * 2016-08-31 2018-03-08 Micron Technology, Inc. Apparatuses and methods including two transistor-one capacitor memory and for accessing same
SG11201901211XA (en) 2016-08-31 2019-03-28 Micron Technology Inc Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory
WO2018044485A1 (en) 2016-08-31 2018-03-08 Micron Technology, Inc. Ferroelectric memory cells
EP3507805A4 (en) 2016-08-31 2020-06-03 Micron Technology, Inc. DEVICES AND METHOD WITH FERROELECTRIC MEMORY AND FOR OPERATING FERROELECTRIC MEMORY
US10867675B2 (en) 2017-07-13 2020-12-15 Micron Technology, Inc. Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells

Family Cites Families (18)

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Publication number Priority date Publication date Assignee Title
JPS58220293A (ja) 1982-06-15 1983-12-21 Nec Corp 記憶装置
JPH0638485B2 (ja) * 1983-06-01 1994-05-18 株式会社日立製作所 半導体メモリ
JPS6111993A (ja) * 1984-06-28 1986-01-20 Toshiba Corp 半導体記憶装置
JPS61120395A (ja) * 1984-11-14 1986-06-07 Toshiba Corp 半導体記憶装置
US5007022A (en) * 1987-12-21 1991-04-09 Texas Instruments Incorporated Two-port two-transistor DRAM
JPH04349295A (ja) * 1991-05-28 1992-12-03 Nec Eng Ltd 半導体記憶素子
KR0135699B1 (ko) * 1994-07-11 1998-04-24 김주용 셀프-리프레쉬 가능한 듀얼포트 동적 캠셀 및 리프레쉬장치
JP2882334B2 (ja) * 1996-01-11 1999-04-12 日本電気株式会社 ダイナミックランダムアクセスメモリ
US5923593A (en) * 1996-12-17 1999-07-13 Monolithic Systems, Inc. Multi-port DRAM cell and memory system using same
US5856940A (en) 1997-08-15 1999-01-05 Silicon Aquarius, Inc. Low latency DRAM cell and method therefor
US6025221A (en) * 1997-08-22 2000-02-15 Micron Technology, Inc. Processing methods of forming integrated circuitry memory devices, methods of forming DRAM arrays, and related semiconductor masks
US6097621A (en) * 1998-05-04 2000-08-01 Texas Instruments Incorporated Memory cell array architecture for random access memory device
US5963497A (en) 1998-05-18 1999-10-05 Silicon Aquarius, Inc. Dynamic random access memory system with simultaneous access and refresh operations and methods for using the same
DE19845124C2 (de) * 1998-09-30 2000-10-26 Siemens Ag Layout für einen Halbleiterspeicher
JP2000124331A (ja) * 1998-10-20 2000-04-28 Matsushita Electric Ind Co Ltd 半導体記憶装置
US6469924B2 (en) 2000-07-14 2002-10-22 Infineon Technologies Ag Memory architecture with refresh and sense amplifiers
US6469925B1 (en) 2000-07-14 2002-10-22 Raj Kumar Jain Memory cell with improved retention time
US6545935B1 (en) * 2000-08-29 2003-04-08 Ibm Corporation Dual-port DRAM architecture system

Also Published As

Publication number Publication date
US6438016B1 (en) 2002-08-20
CN100559504C (zh) 2009-11-11
WO2002019341A2 (en) 2002-03-07
WO2002019341A3 (en) 2003-04-03
CN1461485A (zh) 2003-12-10
KR100702355B1 (ko) 2007-04-04
EP1323168A2 (en) 2003-07-02
JP2004508654A (ja) 2004-03-18
US20020048209A1 (en) 2002-04-25
US20030067829A1 (en) 2003-04-10
EP2287849A3 (en) 2011-03-09
US6757200B2 (en) 2004-06-29
EP2287849A2 (en) 2011-02-23
KR20030045049A (ko) 2003-06-09

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