ATE94667T1 - Geraet zur pufferung von schreibanforderungen. - Google Patents

Geraet zur pufferung von schreibanforderungen.

Info

Publication number
ATE94667T1
ATE94667T1 AT86310038T AT86310038T ATE94667T1 AT E94667 T1 ATE94667 T1 AT E94667T1 AT 86310038 T AT86310038 T AT 86310038T AT 86310038 T AT86310038 T AT 86310038T AT E94667 T1 ATE94667 T1 AT E94667T1
Authority
AT
Austria
Prior art keywords
rank
buffer
write request
write requests
data
Prior art date
Application number
AT86310038T
Other languages
English (en)
Inventor
Marvin Anson Mills Jr
Lester Martin Crudele
Original Assignee
Mips Computer Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mips Computer Systems Inc filed Critical Mips Computer Systems Inc
Application granted granted Critical
Publication of ATE94667T1 publication Critical patent/ATE94667T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)
AT86310038T 1986-05-05 1986-12-22 Geraet zur pufferung von schreibanforderungen. ATE94667T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/860,304 US4805098A (en) 1986-05-05 1986-05-05 Write buffer
EP86310038A EP0244540B1 (de) 1986-05-05 1986-12-22 Gerät zur Pufferung von Schreibanforderungen

Publications (1)

Publication Number Publication Date
ATE94667T1 true ATE94667T1 (de) 1993-10-15

Family

ID=25332918

Family Applications (1)

Application Number Title Priority Date Filing Date
AT86310038T ATE94667T1 (de) 1986-05-05 1986-12-22 Geraet zur pufferung von schreibanforderungen.

Country Status (5)

Country Link
US (1) US4805098A (de)
EP (1) EP0244540B1 (de)
JP (1) JPS62262160A (de)
AT (1) ATE94667T1 (de)
DE (1) DE3689042T2 (de)

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US5963981A (en) * 1995-10-06 1999-10-05 Silicon Graphics, Inc. System and method for uncached store buffering in a microprocessor
US5911051A (en) * 1996-03-29 1999-06-08 Intel Corporation High-throughput interconnect allowing bus transactions based on partial access requests
US6317803B1 (en) 1996-03-29 2001-11-13 Intel Corporation High-throughput interconnect having pipelined and non-pipelined bus transaction modes
US5860091A (en) * 1996-06-28 1999-01-12 Symbios, Inc. Method and apparatus for efficient management of non-aligned I/O write request in high bandwidth raid applications
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US6434641B1 (en) * 1999-05-28 2002-08-13 Unisys Corporation System for reducing the number of requests presented to a main memory in a memory storage system employing a directory-based caching scheme
US6678803B2 (en) * 1999-11-03 2004-01-13 Micron Technology, Inc. Method and device to use memory access request tags
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US7159041B2 (en) * 2000-03-07 2007-01-02 Microsoft Corporation Method and system for defining and controlling algorithmic elements in a graphics display system
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JP4649257B2 (ja) * 2005-04-04 2011-03-09 キヤノン株式会社 マルチｃｐｕシステム
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TWI396975B (zh) * 2008-08-06 2013-05-21 Realtek Semiconductor Corp 可調適緩衝裝置及其方法
US8489794B2 (en) * 2010-03-12 2013-07-16 Lsi Corporation Processor bus bridge for network processors or the like
US9444757B2 (en) 2009-04-27 2016-09-13 Intel Corporation Dynamic configuration of processing modules in a network communications processor architecture
US9461930B2 (en) 2009-04-27 2016-10-04 Intel Corporation Modifying data streams without reordering in a multi-thread, multi-flow network processor
US8949500B2 (en) * 2011-08-08 2015-02-03 Lsi Corporation Non-blocking processor bus bridge for network processors or the like
US8850114B2 (en) * 2010-09-07 2014-09-30 Daniel L Rosenband Storage array controller for flash-based storage devices
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Also Published As

Publication number Publication date
JPS62262160A (ja) 1987-11-14
EP0244540A3 (en) 1988-10-26
US4805098A (en) 1989-02-14
DE3689042T2 (de) 1994-01-27
EP0244540A2 (de) 1987-11-11
DE3689042D1 (de) 1993-10-21
JPH0461383B2 (de) 1992-09-30
EP0244540B1 (de) 1993-09-15

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