ATE511702T1 - Seitenwandporenabdichtung für nichtleiter mit niedriger dielektrizitätskonstante - Google Patents
Seitenwandporenabdichtung für nichtleiter mit niedriger dielektrizitätskonstanteInfo
- Publication number
- ATE511702T1 ATE511702T1 AT06727680T AT06727680T ATE511702T1 AT E511702 T1 ATE511702 T1 AT E511702T1 AT 06727680 T AT06727680 T AT 06727680T AT 06727680 T AT06727680 T AT 06727680T AT E511702 T1 ATE511702 T1 AT E511702T1
- Authority
- AT
- Austria
- Prior art keywords
- porogen
- low
- ulk
- opening
- porous
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
- H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
- H01L2221/1063—Sacrificial or temporary thin dielectric films in openings in a dielectric
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05300202 | 2005-03-22 | ||
PCT/IB2006/050846 WO2006100632A1 (en) | 2005-03-22 | 2006-03-20 | Side wall pore sealing for low-k dielectrics |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE511702T1 true ATE511702T1 (de) | 2011-06-15 |
Family
ID=36580391
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT06727680T ATE511702T1 (de) | 2005-03-22 | 2006-03-20 | Seitenwandporenabdichtung für nichtleiter mit niedriger dielektrizitätskonstante |
Country Status (6)
Country | Link |
---|---|
US (1) | US8445382B2 (de) |
EP (1) | EP1864322B1 (de) |
JP (1) | JP2008535212A (de) |
CN (1) | CN100565833C (de) |
AT (1) | ATE511702T1 (de) |
WO (1) | WO2006100632A1 (de) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8058183B2 (en) * | 2008-06-23 | 2011-11-15 | Applied Materials, Inc. | Restoring low dielectric constant film properties |
JP5147751B2 (ja) * | 2009-02-06 | 2013-02-20 | パナソニック株式会社 | 半導体装置の製造方法 |
US8304863B2 (en) | 2010-02-09 | 2012-11-06 | International Business Machines Corporation | Electromigration immune through-substrate vias |
JP5636277B2 (ja) * | 2010-12-27 | 2014-12-03 | 富士フイルム株式会社 | 多孔質絶縁膜及びその製造方法 |
US20130171819A1 (en) * | 2011-12-28 | 2013-07-04 | Toshiba America Electronic Components, Inc. | Methods for integration of metal/dielectric interconnects |
US8871639B2 (en) * | 2013-01-04 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
CN104143524A (zh) * | 2013-05-07 | 2014-11-12 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
US8932934B2 (en) * | 2013-05-28 | 2015-01-13 | Global Foundries Inc. | Methods of self-forming barrier integration with pore stuffed ULK material |
US20150091172A1 (en) * | 2013-10-01 | 2015-04-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Pore sealing techniques for porous low-k dielectric interconnect |
KR102110247B1 (ko) | 2013-11-29 | 2020-05-13 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그 제조방법 |
US9093387B1 (en) | 2014-01-08 | 2015-07-28 | International Business Machines Corporation | Metallic mask patterning process for minimizing collateral etch of an underlayer |
KR102272553B1 (ko) | 2015-01-19 | 2021-07-02 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
WO2017052559A1 (en) * | 2015-09-24 | 2017-03-30 | Intel Corporation | Methods, apparatuses and systems for integrated circuit structures with a replacement inter-layer dielectric (ild) |
CN105390384B (zh) * | 2015-10-29 | 2018-05-01 | 上海集成电路研发中心有限公司 | 一种无应力电化学抛光铜时去除二氧化硅的方法 |
US9685366B1 (en) * | 2016-04-21 | 2017-06-20 | International Business Machines Corporation | Forming chamferless vias using thermally decomposable porefiller |
US10867843B2 (en) * | 2016-12-05 | 2020-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and system for fabrication semiconductor device |
JP7067424B2 (ja) * | 2017-12-27 | 2022-05-16 | 東京エレクトロン株式会社 | エッチング方法及びエッチング装置 |
US11361974B2 (en) | 2020-09-10 | 2022-06-14 | United Microelectronics Corp. | Method for forming semiconductor structure |
CN117500923A (zh) | 2021-04-07 | 2024-02-02 | 巴特尔纪念研究院 | 用于鉴定和使用非病毒载体的快速设计、构建、测试和学习技术 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6703324B2 (en) | 2000-12-21 | 2004-03-09 | Intel Corporation | Mechanically reinforced highly porous low dielectric constant films |
US6528409B1 (en) | 2002-04-29 | 2003-03-04 | Advanced Micro Devices, Inc. | Interconnect structure formed in porous dielectric material with minimized degradation and electromigration |
JP2004274020A (ja) | 2002-09-24 | 2004-09-30 | Rohm & Haas Electronic Materials Llc | 電子デバイス製造 |
JP2004200203A (ja) | 2002-12-16 | 2004-07-15 | Semiconductor Leading Edge Technologies Inc | 半導体装置及びその製造方法 |
US7157373B2 (en) * | 2003-12-11 | 2007-01-02 | Infineon Technologies Ag | Sidewall sealing of porous dielectric materials |
JP2005197606A (ja) | 2004-01-09 | 2005-07-21 | Toshiba Corp | 半導体装置およびその製造方法 |
-
2006
- 2006-03-20 EP EP06727680A patent/EP1864322B1/de active Active
- 2006-03-20 US US11/909,442 patent/US8445382B2/en active Active
- 2006-03-20 JP JP2008502539A patent/JP2008535212A/ja not_active Withdrawn
- 2006-03-20 AT AT06727680T patent/ATE511702T1/de not_active IP Right Cessation
- 2006-03-20 WO PCT/IB2006/050846 patent/WO2006100632A1/en active Application Filing
- 2006-03-20 CN CNB2006800089678A patent/CN100565833C/zh active Active
Also Published As
Publication number | Publication date |
---|---|
WO2006100632A1 (en) | 2006-09-28 |
US20090321945A1 (en) | 2009-12-31 |
EP1864322A1 (de) | 2007-12-12 |
JP2008535212A (ja) | 2008-08-28 |
US8445382B2 (en) | 2013-05-21 |
CN101164160A (zh) | 2008-04-16 |
EP1864322B1 (de) | 2011-06-01 |
CN100565833C (zh) | 2009-12-02 |
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Legal Events
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RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |