ATE490599T1 - Verfahren und vorrichtung für einen n-nary logischer stromkreis - Google Patents
Verfahren und vorrichtung für einen n-nary logischer stromkreisInfo
- Publication number
- ATE490599T1 ATE490599T1 AT99966138T AT99966138T ATE490599T1 AT E490599 T1 ATE490599 T1 AT E490599T1 AT 99966138 T AT99966138 T AT 99966138T AT 99966138 T AT99966138 T AT 99966138T AT E490599 T1 ATE490599 T1 AT E490599T1
- Authority
- AT
- Austria
- Prior art keywords
- nary
- signals
- present
- shared logic
- circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
- G06F5/015—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising having at least two separately controlled shifting levels, e.g. using shifting matrices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
- G06F7/026—Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/418—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0002—Multistate logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/0813—Threshold logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
- H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3812—Devices capable of handling different types of numbers
- G06F2207/3824—Accepting both fixed-point and floating-point numbers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
- G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/019,244 US6069497A (en) | 1997-12-11 | 1998-02-05 | Method and apparatus for a N-nary logic circuit using 1 of N signals |
PCT/US1999/029409 WO2001043287A1 (en) | 1998-02-05 | 1999-12-10 | Method and apparatus for an n-nary logic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE490599T1 true ATE490599T1 (de) | 2010-12-15 |
Family
ID=21792195
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT99966138T ATE490599T1 (de) | 1998-02-05 | 1999-12-10 | Verfahren und vorrichtung für einen n-nary logischer stromkreis |
Country Status (4)
Country | Link |
---|---|
US (2) | US6069497A (de) |
EP (2) | EP1236278B1 (de) |
AT (1) | ATE490599T1 (de) |
WO (2) | WO2001043287A1 (de) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6460134B1 (en) * | 1997-12-03 | 2002-10-01 | Intrinsity, Inc. | Method and apparatus for a late pipeline enhanced floating point unit |
DE69834431T3 (de) * | 1998-01-02 | 2009-09-10 | Cryptography Research Inc., San Francisco | Leckresistentes kryptographisches verfahren und vorrichtung |
US7587044B2 (en) | 1998-01-02 | 2009-09-08 | Cryptography Research, Inc. | Differential power analysis method and apparatus |
IL139935A (en) | 1998-06-03 | 2005-06-19 | Cryptography Res Inc | Des and other cryptographic processes with leak minimization for smartcards and other cryptosystems |
DE69935913T2 (de) * | 1998-07-02 | 2008-01-10 | Cryptography Research Inc., San Francisco | Leckresistente aktualisierung eines indexierten kryptographischen schlüssels |
US6275840B1 (en) * | 1998-12-10 | 2001-08-14 | Intel Corporation | Fast overflow detection in decoded bit-vector addition |
US7099812B2 (en) * | 1999-09-24 | 2006-08-29 | Intrinsity, Inc. | Grid that tracks the occurrence of a N-dimensional matrix of combinatorial events in a simulation using a linear index |
US6633992B1 (en) * | 1999-12-30 | 2003-10-14 | Intel Corporation | Generalized pre-charge clock circuit for pulsed domino gates |
JP2002118176A (ja) * | 2000-10-05 | 2002-04-19 | Nec Corp | 半導体装置 |
US6714045B2 (en) * | 2001-07-02 | 2004-03-30 | Intrinsity, Inc. | Static transmission of FAST14 logic 1-of-N signals |
US6956406B2 (en) * | 2001-07-02 | 2005-10-18 | Intrinsity, Inc. | Static storage element for dynamic logic |
US7053664B2 (en) * | 2001-07-02 | 2006-05-30 | Intrinsity, Inc. | Null value propagation for FAST14 logic |
DE10217375B4 (de) * | 2002-04-18 | 2006-08-24 | Infineon Technologies Ag | Schaltungsanordnung und Verfahren zur Erzeugung eines Dual-Rail-Signals |
US7103832B2 (en) * | 2003-12-04 | 2006-09-05 | International Business Machines Corporation | Scalable cyclic redundancy check circuit |
DE102005037357B3 (de) * | 2005-08-08 | 2007-02-01 | Infineon Technologies Ag | Logikschaltung und Verfahren zum Berechnen eines maskierten Ergebnisoperanden |
US7881465B2 (en) * | 2005-08-08 | 2011-02-01 | Infineon Technologies Ag | Circuit and method for calculating a logic combination of two encrypted input operands |
US20080043406A1 (en) * | 2006-08-16 | 2008-02-21 | Secure Computing Corporation | Portable computer security device that includes a clip |
US8482315B2 (en) | 2011-08-23 | 2013-07-09 | Apple Inc. | One-of-n N-nary logic implementation of a storage cell |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2958724A (en) * | 1958-11-28 | 1960-11-01 | Perfection Mica Company | Electrical connector |
US5208489A (en) * | 1986-09-03 | 1993-05-04 | Texas Instruments Incorporated | Multiple compound domino logic circuit |
US4851714A (en) * | 1987-12-11 | 1989-07-25 | American Telephone And Telgraph Company, At&T Bell Laboratories | Multiple output field effect transistor logic |
JPH04109488A (ja) * | 1990-08-29 | 1992-04-10 | Mitsubishi Electric Corp | ダイナミック型半導体記憶装置 |
US5208490A (en) * | 1991-04-12 | 1993-05-04 | Hewlett-Packard Company | Functionally complete family of self-timed dynamic logic circuits |
JP3014238B2 (ja) * | 1993-04-28 | 2000-02-28 | 富士通株式会社 | 可変論理演算装置 |
US5524088A (en) * | 1993-06-30 | 1996-06-04 | Sharp Kabushiki Kaisha | Multi-functional operating circuit providing capability of freely combining operating functions |
JP2768298B2 (ja) * | 1995-03-30 | 1998-06-25 | 日本電気株式会社 | 論理回路 |
US5640108A (en) * | 1995-06-07 | 1997-06-17 | International Business Machines Corporation | Single stage dynamic receiver/decoder |
US5666525A (en) | 1995-09-21 | 1997-09-09 | The Trustees Of Columbia University In The City Of New York | System and method for performing an efficient join operation on large tables with a small main memory |
JPH0991962A (ja) * | 1995-09-26 | 1997-04-04 | Texas Instr Japan Ltd | アドレスデコーダ |
US5596539A (en) * | 1995-12-28 | 1997-01-21 | Lsi Logic Corporation | Method and apparatus for a low power self-timed memory control system |
FR2745117B1 (fr) * | 1996-02-21 | 2000-10-13 | Whitaker Corp | Cable flexible et souple a helices espacees |
JPH09251782A (ja) * | 1996-03-14 | 1997-09-22 | Fujitsu Ltd | 半導体記憶装置 |
JPH09320286A (ja) * | 1996-05-24 | 1997-12-12 | Nec Corp | 半導体記憶装置 |
US5682353A (en) * | 1996-06-13 | 1997-10-28 | Waferscale Integration Inc. | Self adjusting sense amplifier clock delay circuit |
US5668525A (en) * | 1996-09-17 | 1997-09-16 | International Business Machines Corporation | Comparator circuit using two bit to four bit encoder |
US5808932A (en) * | 1996-12-23 | 1998-09-15 | Lsi Logic Corporation | Memory system which enables storage and retrieval of more than two states in a memory cell |
JP3862346B2 (ja) * | 1997-03-13 | 2006-12-27 | 富士通株式会社 | 駆動回路及びそれを利用した半導体記憶装置 |
US5867423A (en) * | 1997-04-10 | 1999-02-02 | Lsi Logic Corporation | Memory circuit and method for multivalued logic storage by process variations |
US5901081A (en) * | 1997-12-18 | 1999-05-04 | Texas Instruments Incorporated | Circuit and method for preconditioning memory word lines across word line boundaries |
-
1998
- 1998-02-05 US US09/019,244 patent/US6069497A/en not_active Expired - Lifetime
-
1999
- 1999-12-10 EP EP99966138A patent/EP1236278B1/de not_active Expired - Lifetime
- 1999-12-10 AT AT99966138T patent/ATE490599T1/de not_active IP Right Cessation
- 1999-12-10 WO PCT/US1999/029409 patent/WO2001043287A1/en active Application Filing
- 1999-12-10 EP EP10179489A patent/EP2293448A3/de not_active Withdrawn
- 1999-12-10 US US09/458,763 patent/US6252425B1/en not_active Expired - Lifetime
- 1999-12-21 WO PCT/US1999/030502 patent/WO2001046988A2/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
EP2293448A2 (de) | 2011-03-09 |
US6252425B1 (en) | 2001-06-26 |
WO2001043287A1 (en) | 2001-06-14 |
WO2001046988A3 (en) | 2007-08-23 |
EP1236278A1 (de) | 2002-09-04 |
US6069497A (en) | 2000-05-30 |
EP1236278B1 (de) | 2010-12-01 |
EP1236278A4 (de) | 2004-11-10 |
EP2293448A3 (de) | 2011-05-04 |
WO2001046988A2 (en) | 2001-06-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |