ATE482404T1 - Sequenzielles multimodales zweiwege- speicherelement - Google Patents
Sequenzielles multimodales zweiwege- speicherelementInfo
- Publication number
- ATE482404T1 ATE482404T1 AT07757747T AT07757747T ATE482404T1 AT E482404 T1 ATE482404 T1 AT E482404T1 AT 07757747 T AT07757747 T AT 07757747T AT 07757747 T AT07757747 T AT 07757747T AT E482404 T1 ATE482404 T1 AT E482404T1
- Authority
- AT
- Austria
- Prior art keywords
- data
- sequential storage
- sequential
- storage element
- output
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/32—Serial access; Scan testing
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/365,716 US7725792B2 (en) | 2006-03-01 | 2006-03-01 | Dual-path, multimode sequential storage element |
| PCT/US2007/063104 WO2007103748A1 (en) | 2006-03-01 | 2007-03-01 | Dual-path, multimode sequential storage element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE482404T1 true ATE482404T1 (de) | 2010-10-15 |
Family
ID=38191244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT07757747T ATE482404T1 (de) | 2006-03-01 | 2007-03-01 | Sequenzielles multimodales zweiwege- speicherelement |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US7725792B2 (de) |
| EP (1) | EP1989562B1 (de) |
| JP (2) | JP5118069B2 (de) |
| KR (1) | KR100963385B1 (de) |
| CN (1) | CN101389970B (de) |
| AT (1) | ATE482404T1 (de) |
| DE (1) | DE602007009365D1 (de) |
| TW (1) | TWI343542B (de) |
| WO (1) | WO2007103748A1 (de) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7725792B2 (en) * | 2006-03-01 | 2010-05-25 | Qualcomm Incorporated | Dual-path, multimode sequential storage element |
| US8089095B2 (en) * | 2008-10-15 | 2012-01-03 | Semiconductor Components Industries, Llc | Two terminal multi-channel ESD device and method therefor |
| US8406077B2 (en) * | 2010-07-01 | 2013-03-26 | Qualcomm Incorporated | Multi-voltage level, multi-dynamic circuit structure device |
| US8829965B2 (en) * | 2012-08-01 | 2014-09-09 | Qualcomm Incorporated | System and method to perform scan testing using a pulse latch with a blocking gate |
| US20200106424A1 (en) * | 2018-09-27 | 2020-04-02 | Apple Inc. | Semi dynamic flop and single stage pulse flop with shadow latch and transparency on both input data edges |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4873456A (en) * | 1988-06-06 | 1989-10-10 | Tektronix, Inc. | High speed state machine |
| US5378934A (en) | 1990-09-12 | 1995-01-03 | Hitachi, Ltd. | Circuit having a master-and-slave and a by-pass |
| JP3138045B2 (ja) * | 1992-01-10 | 2001-02-26 | 株式会社日立製作所 | 半導体集積回路 |
| US5617549A (en) * | 1992-10-06 | 1997-04-01 | Hewlett-Packard Co | System and method for selecting and buffering even and odd instructions for simultaneous execution in a computer |
| JPH0795013A (ja) * | 1993-04-30 | 1995-04-07 | Kawasaki Steel Corp | エッジトリガ型フリップフロップ |
| JPH07254756A (ja) * | 1994-03-15 | 1995-10-03 | Sony Corp | 光デバイス |
| US5424654A (en) | 1994-09-22 | 1995-06-13 | Kaplinsky; Cecil H. | Programmable macrocell circuit |
| US6438720B1 (en) * | 1995-06-07 | 2002-08-20 | Texas Instruments Incorporated | Host port interface |
| US6362015B1 (en) * | 1998-10-30 | 2002-03-26 | Texas Instruments Incorporated | Process of making an integrated circuit using parallel scan paths |
| US6242269B1 (en) * | 1997-11-03 | 2001-06-05 | Texas Instruments Incorporated | Parallel scan distributors and collectors and process of testing integrated circuits |
| FR2793628A1 (fr) * | 1999-05-11 | 2000-11-17 | Koninkl Philips Electronics Nv | Systeme de transmission, recepteur et reseau d'interconnexion |
| US6662324B1 (en) * | 1999-12-28 | 2003-12-09 | International Business Machines Corporation | Global transition scan based AC method |
| KR100319897B1 (ko) * | 2000-01-31 | 2002-01-10 | 윤종용 | 파이프라인 구조에서의 데이터 테스트 시간을 줄일 수있는 반도체 메모리장치 |
| US7535772B1 (en) * | 2003-06-27 | 2009-05-19 | Cypress Semiconductor Corporation | Configurable data path architecture and clocking scheme |
| JP3869406B2 (ja) * | 2003-11-10 | 2007-01-17 | 株式会社東芝 | クロック位相差検出回路、クロック分配回路、及び大規模集積回路 |
| JP2005303464A (ja) * | 2004-04-07 | 2005-10-27 | Toshiba Corp | フリップフロップ |
| US7725792B2 (en) * | 2006-03-01 | 2010-05-25 | Qualcomm Incorporated | Dual-path, multimode sequential storage element |
-
2006
- 2006-03-01 US US11/365,716 patent/US7725792B2/en active Active
-
2007
- 2007-03-01 JP JP2008557503A patent/JP5118069B2/ja active Active
- 2007-03-01 TW TW096107069A patent/TWI343542B/zh not_active IP Right Cessation
- 2007-03-01 WO PCT/US2007/063104 patent/WO2007103748A1/en active Application Filing
- 2007-03-01 EP EP07757747A patent/EP1989562B1/de not_active Not-in-force
- 2007-03-01 CN CN2007800069679A patent/CN101389970B/zh not_active Expired - Fee Related
- 2007-03-01 AT AT07757747T patent/ATE482404T1/de not_active IP Right Cessation
- 2007-03-01 DE DE602007009365T patent/DE602007009365D1/de active Active
- 2007-03-01 KR KR1020087024012A patent/KR100963385B1/ko active IP Right Grant
-
2012
- 2012-07-06 JP JP2012152627A patent/JP5631934B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP1989562B1 (de) | 2010-09-22 |
| TW200802084A (en) | 2008-01-01 |
| CN101389970A (zh) | 2009-03-18 |
| KR20080110770A (ko) | 2008-12-19 |
| CN101389970B (zh) | 2011-06-15 |
| WO2007103748A9 (en) | 2007-11-15 |
| KR100963385B1 (ko) | 2010-06-14 |
| JP2012217201A (ja) | 2012-11-08 |
| US7725792B2 (en) | 2010-05-25 |
| WO2007103748A1 (en) | 2007-09-13 |
| JP5118069B2 (ja) | 2013-01-16 |
| JP5631934B2 (ja) | 2014-11-26 |
| DE602007009365D1 (de) | 2010-11-04 |
| US20070208912A1 (en) | 2007-09-06 |
| TWI343542B (en) | 2011-06-11 |
| JP2009528799A (ja) | 2009-08-06 |
| EP1989562A1 (de) | 2008-11-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |