ATE532267T1 - Verzögerungsregelschleife - Google Patents

Verzögerungsregelschleife

Info

Publication number
ATE532267T1
ATE532267T1 AT06780203T AT06780203T ATE532267T1 AT E532267 T1 ATE532267 T1 AT E532267T1 AT 06780203 T AT06780203 T AT 06780203T AT 06780203 T AT06780203 T AT 06780203T AT E532267 T1 ATE532267 T1 AT E532267T1
Authority
AT
Austria
Prior art keywords
delay
clock
input
receiving
locked
Prior art date
Application number
AT06780203T
Other languages
English (en)
Inventor
Pavel Petkov
Jim Conder
Friedel Gerfers
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE532267T1 publication Critical patent/ATE532267T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
AT06780203T 2005-08-03 2006-07-25 Verzögerungsregelschleife ATE532267T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05107151 2005-08-03
PCT/IB2006/052550 WO2007015191A1 (en) 2005-08-03 2006-07-25 Delay-locked loop

Publications (1)

Publication Number Publication Date
ATE532267T1 true ATE532267T1 (de) 2011-11-15

Family

ID=37460355

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06780203T ATE532267T1 (de) 2005-08-03 2006-07-25 Verzögerungsregelschleife

Country Status (5)

Country Link
EP (1) EP1913696B1 (de)
JP (1) JP2009504058A (de)
CN (1) CN101233689A (de)
AT (1) ATE532267T1 (de)
WO (1) WO2007015191A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8384456B1 (en) * 2011-11-18 2013-02-26 Texas Instruments Incorporated Integrated phase-locked and multiplying delay-locked loop with spur cancellation
CN103065172B (zh) * 2012-12-26 2015-09-16 广州中大微电子有限公司 一种rfid读写器的接收端电路及其实现方法
US9203387B2 (en) 2014-02-24 2015-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Delay line circuit with variable delay line unit
KR101938674B1 (ko) * 2017-11-27 2019-01-15 주식회사 아나패스 위상 고정 루프 및 지연 고정 루프
CN109088622B (zh) * 2018-08-02 2023-10-31 深圳市精嘉微电子有限公司 一种细粒度延迟输出控制的电路和方法
KR20230087027A (ko) 2021-12-09 2023-06-16 주식회사 엘엑스세미콘 디스플레이의 클럭 복원 회로

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7346139B2 (en) * 2002-10-11 2008-03-18 Agere Systems Inc. Circuit and method for generating a local clock signal

Also Published As

Publication number Publication date
EP1913696A1 (de) 2008-04-23
JP2009504058A (ja) 2009-01-29
CN101233689A (zh) 2008-07-30
WO2007015191A1 (en) 2007-02-08
EP1913696B1 (de) 2011-11-02

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