DE602007013023D1 - Testzugangsportschalter - Google Patents

Testzugangsportschalter

Info

Publication number
DE602007013023D1
DE602007013023D1 DE602007013023T DE602007013023T DE602007013023D1 DE 602007013023 D1 DE602007013023 D1 DE 602007013023D1 DE 602007013023 T DE602007013023 T DE 602007013023T DE 602007013023 T DE602007013023 T DE 602007013023T DE 602007013023 D1 DE602007013023 D1 DE 602007013023D1
Authority
DE
Germany
Prior art keywords
tap
switch
tap switch
electronic system
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007013023T
Other languages
English (en)
Inventor
Kevin Charles Burke
Philip Richard Pottier
Srinivas Varadarajan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of DE602007013023D1 publication Critical patent/DE602007013023D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Push-Button Switches (AREA)
  • Vehicle Body Suspensions (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Information Transfer Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE602007013023T 2006-04-12 2007-04-12 Testzugangsportschalter Active DE602007013023D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/402,431 US20070255990A1 (en) 2006-04-12 2006-04-12 Test access port switch
PCT/US2007/066577 WO2007121330A1 (en) 2006-04-12 2007-04-12 Test access port switch

Publications (1)

Publication Number Publication Date
DE602007013023D1 true DE602007013023D1 (de) 2011-04-21

Family

ID=38476891

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007013023T Active DE602007013023D1 (de) 2006-04-12 2007-04-12 Testzugangsportschalter

Country Status (8)

Country Link
US (1) US20070255990A1 (de)
EP (1) EP2010927B1 (de)
JP (2) JP2009533691A (de)
KR (1) KR20090023346A (de)
CN (1) CN101421633B (de)
AT (1) ATE501439T1 (de)
DE (1) DE602007013023D1 (de)
WO (1) WO2007121330A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7877653B2 (en) * 2007-05-09 2011-01-25 Texas Instruments Incorporated Address and TMS gating circuitry for TAP control circuit
JP5022110B2 (ja) * 2007-06-05 2012-09-12 ルネサスエレクトロニクス株式会社 半導体集積回路
US7895300B1 (en) * 2008-02-28 2011-02-22 Qlogic, Corporation Systems and methods for testing device ports in a storage area network
EP2141597B1 (de) * 2008-07-03 2010-12-29 Renesas Electronics Corporation Integrierte Halbleiterschaltung
US20120324302A1 (en) * 2011-06-17 2012-12-20 Qualcomm Incorporated Integrated circuit for testing using a high-speed input/output interface
JP5983171B2 (ja) * 2012-08-10 2016-08-31 株式会社Ｇｓユアサ スイッチ故障診断装置、蓄電装置
CN109085496B (zh) * 2012-08-10 2020-11-03 株式会社杰士汤浅国际 开关故障诊断装置及蓄电装置
CN103809104B (zh) * 2012-11-09 2017-03-01 瑞昱半导体股份有限公司 扫描时脉产生器以及扫描时脉产生方法
CN105721917B (zh) * 2016-02-24 2018-08-07 浪潮软件集团有限公司 一种端口复用的电路及数字电视机顶盒
CN108205087A (zh) * 2016-12-20 2018-06-26 中国航天科工集团八五研究所 一种具有计时功能的全自动测试系统
US10395691B1 (en) * 2017-08-18 2019-08-27 Seagate Technology Llc Device configured to switch a test system channel between multiple drive controllers
CN107729614A (zh) * 2017-09-18 2018-02-23 北京空间飞行器总体设计部 一种可扩展的通用功能级异步电路
US20190242941A1 (en) * 2018-02-06 2019-08-08 Marvell World Trade Ltd. Methods and Apparatus for Testing an Integrated Circuit
CN112416482B (zh) * 2019-08-23 2024-04-23 钉钉控股（开曼）有限公司 界面切换方法及装置
US11789067B1 (en) * 2020-02-07 2023-10-17 Marvell Israel (M.I.S.L) Ltd. Physical layer parameter compliance in high speed communication networks
CN112290932B (zh) * 2020-09-30 2022-09-06 上海兆芯集成电路有限公司 电路及其测试电路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2278259B (en) * 1993-05-21 1997-01-15 Northern Telecom Ltd Serial bus system
US6324662B1 (en) * 1996-08-30 2001-11-27 Texas Instruments Incorporated TAP and linking module for scan access of multiple cores with IEEE 1149.1 test access ports
US5761129A (en) * 1997-03-25 1998-06-02 Adaptec, Inc. Method and apparatus for I/O multiplexing of RAM bus
US5982684A (en) * 1998-05-28 1999-11-09 Intel Corporation Parallel access testing of a memory array
JP4627865B2 (ja) * 2000-11-07 2011-02-09 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US6686759B1 (en) * 2000-11-28 2004-02-03 Cadence Design Systems, Inc. Techniques for testing embedded cores in multi-core integrated circuit designs
KR20030082135A (ko) * 2002-04-16 2003-10-22 삼성전자주식회사 반도체 소자의 테스트 프로그램 에뮬레이터 및 에뮬레이션방법
US7134061B2 (en) * 2003-09-08 2006-11-07 Texas Instruments Incorporated At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform
EP1992955B1 (de) * 2003-12-17 2012-07-25 STMicroelectronics (Research & Development) Limited TAP-Multiplexer
US7284172B2 (en) * 2004-04-30 2007-10-16 International Business Machines Corporation Access method for embedded JTAG TAP controller instruction registers
CN100372318C (zh) * 2005-05-20 2008-02-27 清华大学 10g网络性能测试系统并行流调度方法
US7506228B2 (en) * 2006-02-14 2009-03-17 Atmel Corporation Measuring the internal clock speed of an integrated circuit

Also Published As

Publication number Publication date
EP2010927A1 (de) 2009-01-07
JP2009533691A (ja) 2009-09-17
CN101421633A (zh) 2009-04-29
US20070255990A1 (en) 2007-11-01
EP2010927B1 (de) 2011-03-09
JP2012088321A (ja) 2012-05-10
KR20090023346A (ko) 2009-03-04
ATE501439T1 (de) 2011-03-15
WO2007121330A1 (en) 2007-10-25
CN101421633B (zh) 2012-10-24

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