ATE479185T1 - Speicher mit selektiver vorladung - Google Patents

Speicher mit selektiver vorladung

Info

Publication number
ATE479185T1
ATE479185T1 AT07799372T AT07799372T ATE479185T1 AT E479185 T1 ATE479185 T1 AT E479185T1 AT 07799372 T AT07799372 T AT 07799372T AT 07799372 T AT07799372 T AT 07799372T AT E479185 T1 ATE479185 T1 AT E479185T1
Authority
AT
Austria
Prior art keywords
memory cells
memory
subset
selective precharge
command
Prior art date
Application number
AT07799372T
Other languages
English (en)
Inventor
G R Rao
Original Assignee
S Aqua Semiconductor Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by S Aqua Semiconductor Llc filed Critical S Aqua Semiconductor Llc
Application granted granted Critical
Publication of ATE479185T1 publication Critical patent/ATE479185T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Saccharide Compounds (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
AT07799372T 2006-07-07 2007-07-06 Speicher mit selektiver vorladung ATE479185T1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US81929606P 2006-07-07 2006-07-07
US81926306P 2006-07-07 2006-07-07
US11/771,895 US7755961B2 (en) 2006-07-07 2007-06-29 Memories with selective precharge
PCT/US2007/072981 WO2008006081A2 (en) 2006-07-07 2007-07-06 Memories with selective precharge

Publications (1)

Publication Number Publication Date
ATE479185T1 true ATE479185T1 (de) 2010-09-15

Family

ID=38895502

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07799372T ATE479185T1 (de) 2006-07-07 2007-07-06 Speicher mit selektiver vorladung

Country Status (8)

Country Link
US (1) US7755961B2 (de)
EP (1) EP2038891B1 (de)
JP (1) JP5767778B2 (de)
KR (1) KR101037637B1 (de)
CN (2) CN101506894B (de)
AT (1) ATE479185T1 (de)
DE (1) DE602007008727D1 (de)
WO (1) WO2008006081A2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
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WO2008006075A2 (en) * 2006-07-07 2008-01-10 S. Aqua Semiconductor, Llc Memories with front end precharge
US7724593B2 (en) * 2006-07-07 2010-05-25 Rao G R Mohan Memories with front end precharge
US7649787B2 (en) * 2006-09-05 2010-01-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7995409B2 (en) * 2007-10-16 2011-08-09 S. Aqua Semiconductor, Llc Memory with independent access and precharge
US8095853B2 (en) 2007-10-19 2012-01-10 S. Aqua Semiconductor Llc Digital memory with fine grain write operation
KR101633399B1 (ko) * 2009-04-27 2016-06-27 삼성전자주식회사 뱅크 프리차지 동작 시에 각 뱅크별 프리차지 동작 시점을 조절할 수 있는 반도체 메모리 장치의 프리차지 방법 및 이 방법을 이용하는 반도체 메모리 장치
JP5671418B2 (ja) * 2010-08-06 2015-02-18 株式会社半導体エネルギー研究所 半導体装置の駆動方法
CN102034544A (zh) * 2010-12-30 2011-04-27 天津南大强芯半导体芯片设计有限公司 一种eeprom存储器电路
US9116781B2 (en) 2011-10-17 2015-08-25 Rambus Inc. Memory controller and memory device command protocol
KR101925018B1 (ko) 2012-06-19 2018-12-05 삼성전자주식회사 불휘발성 메모리 장치
KR20140029024A (ko) * 2012-08-31 2014-03-10 에스케이하이닉스 주식회사 매립 게이트형 무접합 반도체 소자와 그 반도체 소자를 갖는 모듈 및 시스템 그리고 그 반도체 소자의 제조 방법
KR102048765B1 (ko) 2013-01-15 2020-01-22 삼성전자주식회사 메모리 시스템의 동작 방법 및 메모리 시스템
US9087604B1 (en) * 2014-04-13 2015-07-21 Nanya Technology Corporation Pre-charging method applied in dynamic random access memories
KR102264207B1 (ko) * 2014-08-27 2021-06-14 삼성전자주식회사 프리차지 제어 신호 발생기 및 그를 구비한 반도체 메모리 장치
US9646660B2 (en) * 2014-09-23 2017-05-09 Intel Corporation Selectable memory access time
US9811420B2 (en) * 2015-03-27 2017-11-07 Intel Corporation Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)
US9613685B1 (en) * 2015-11-13 2017-04-04 Texas Instruments Incorporated Burst mode read controllable SRAM
CN107180649B (zh) * 2016-03-11 2021-01-15 联华电子股份有限公司 半导体存储器元件及操作半导体存储器元件的方法
US9953701B1 (en) * 2017-02-22 2018-04-24 Arm Limited SRAM architecture with bitcells of varying speed and density
US10210923B2 (en) 2017-07-12 2019-02-19 International Business Machines Corporation Activation of memory core circuits in an integrated circuit
US11114155B2 (en) * 2019-01-24 2021-09-07 Marvell Asia Pte, Ltd. High-density high-bandwidth static random access memory (SRAM) with phase shifted sequential read
GB2582636B (en) 2019-03-29 2023-02-08 Paulet Melmoth Walters Christopher A linear vibration damper
US11587610B2 (en) * 2021-05-28 2023-02-21 Microsoft Technology Licensing, Llc Memory having flying bitlines for improved burst mode read operations

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JPS61126683A (ja) 1984-11-22 1986-06-14 Toshiba Corp 半導体メモリ装置
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JP2999869B2 (ja) * 1991-11-15 2000-01-17 沖電気工業株式会社 メモリアクセス方式
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FR2874734A1 (fr) * 2004-08-26 2006-03-03 St Microelectronics Sa Procede de lecture de cellules memoire programmables et effacables electriquement, a precharge anticipee de lignes de bit
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WO2008006075A2 (en) * 2006-07-07 2008-01-10 S. Aqua Semiconductor, Llc Memories with front end precharge
US7995409B2 (en) * 2007-10-16 2011-08-09 S. Aqua Semiconductor, Llc Memory with independent access and precharge

Also Published As

Publication number Publication date
EP2038891A4 (de) 2009-09-09
JP5767778B2 (ja) 2015-08-19
WO2008006081A3 (en) 2008-09-18
DE602007008727D1 (de) 2010-10-07
CN103000217B (zh) 2016-04-20
CN101506894A (zh) 2009-08-12
EP2038891B1 (de) 2010-08-25
KR20090038451A (ko) 2009-04-20
CN103000217A (zh) 2013-03-27
JP2009543270A (ja) 2009-12-03
US7755961B2 (en) 2010-07-13
WO2008006081A2 (en) 2008-01-10
US20080123451A1 (en) 2008-05-29
EP2038891A2 (de) 2009-03-25
KR101037637B1 (ko) 2011-05-30
CN101506894B (zh) 2012-10-03

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