ATE459982T1 - Verfahren und vorrichtung zum herstellen eines gebondeten dielektrischen trennungswafers - Google Patents

Verfahren und vorrichtung zum herstellen eines gebondeten dielektrischen trennungswafers

Info

Publication number
ATE459982T1
ATE459982T1 AT01908349T AT01908349T ATE459982T1 AT E459982 T1 ATE459982 T1 AT E459982T1 AT 01908349 T AT01908349 T AT 01908349T AT 01908349 T AT01908349 T AT 01908349T AT E459982 T1 ATE459982 T1 AT E459982T1
Authority
AT
Austria
Prior art keywords
wafer
wafers
producing
dielectric separation
orientation flat
Prior art date
Application number
AT01908349T
Other languages
English (en)
Inventor
Hiroyuki Oi
Hitoshi Okuda
Original Assignee
Sumco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corp filed Critical Sumco Corp
Application granted granted Critical
Publication of ATE459982T1 publication Critical patent/ATE459982T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
    • H10P72/53—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1922—Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Element Separation (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AT01908349T 2000-04-28 2001-03-05 Verfahren und vorrichtung zum herstellen eines gebondeten dielektrischen trennungswafers ATE459982T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000130790A JP3991300B2 (ja) 2000-04-28 2000-04-28 張り合わせ誘電体分離ウェーハの製造方法
PCT/JP2001/001728 WO2001084633A1 (en) 2000-04-28 2001-03-05 Method and apparatus for producing bonded dielectric separation wafer

Publications (1)

Publication Number Publication Date
ATE459982T1 true ATE459982T1 (de) 2010-03-15

Family

ID=18639812

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01908349T ATE459982T1 (de) 2000-04-28 2001-03-05 Verfahren und vorrichtung zum herstellen eines gebondeten dielektrischen trennungswafers

Country Status (7)

Country Link
US (1) US6830985B2 (de)
EP (1) EP1278245B1 (de)
JP (1) JP3991300B2 (de)
AT (1) ATE459982T1 (de)
DE (1) DE60141462D1 (de)
TW (1) TW483042B (de)
WO (1) WO2001084633A1 (de)

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TWI272654B (en) * 2003-07-18 2007-02-01 Asia Pacific Microsystems Inc Method for keeping the precision of photolithography alignment after wafer bonding
FR2860842B1 (fr) * 2003-10-14 2007-11-02 Tracit Technologies Procede de preparation et d'assemblage de substrats
KR101256711B1 (ko) * 2004-01-07 2013-04-19 가부시키가이샤 니콘 적층 장치 및 집적 회로 소자의 적층 방법
DE102004007060B3 (de) 2004-02-13 2005-07-07 Thallner, Erich, Dipl.-Ing. Vorrichtung und Verfahren zum Verbinden von Wafern
DE102004012618B3 (de) 2004-03-12 2005-10-27 Erich Dipl.-Ing. Thallner Vorrichtung und Verfahren zum Aufbringen einer Folie auf eine Kontaktfläche eines Wafers
US7402520B2 (en) * 2004-11-26 2008-07-22 Applied Materials, Inc. Edge removal of silicon-on-insulator transfer wafer
US7442476B2 (en) 2004-12-27 2008-10-28 Asml Netherlands B.V. Method and system for 3D alignment in wafer scale integration
FR2880184B1 (fr) * 2004-12-28 2007-03-30 Commissariat Energie Atomique Procede de detourage d'une structure obtenue par assemblage de deux plaques
FR2899594A1 (fr) 2006-04-10 2007-10-12 Commissariat Energie Atomique Procede d'assemblage de substrats avec traitements thermiques a basses temperatures
JP4820801B2 (ja) 2006-12-26 2011-11-24 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの製造方法
US7875528B2 (en) * 2007-02-07 2011-01-25 International Business Machines Corporation Method, system, program product for bonding two circuitry-including substrates and related stage
JP5343847B2 (ja) * 2007-06-12 2013-11-13 株式会社ニコン ウェハ貼り合せ装置、ウェハ貼り合せ方法
US7875529B2 (en) * 2007-10-05 2011-01-25 Micron Technology, Inc. Semiconductor devices
US7927938B2 (en) * 2007-11-19 2011-04-19 Micron Technology, Inc. Fin-JFET
US8139219B2 (en) * 2008-04-02 2012-03-20 Suss Microtec Lithography, Gmbh Apparatus and method for semiconductor wafer alignment
JP5342210B2 (ja) * 2008-10-30 2013-11-13 三菱重工業株式会社 アライメント装置制御装置およびアライメント方法
JP5564785B2 (ja) * 2008-12-08 2014-08-06 株式会社Ｓｕｍｃｏ 貼り合わせ基板の製造方法
FR2941302B1 (fr) * 2009-01-19 2011-04-15 Soitec Silicon On Insulator Procede de test sur le substrat support d'un substrat de type "semi-conducteur sur isolant".
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
EP3731258A1 (de) 2009-09-22 2020-10-28 EV Group E. Thallner GmbH Vorrichtung zum ausrichten zweier substrate
FR2950734B1 (fr) * 2009-09-28 2011-12-09 Soitec Silicon On Insulator Procede de collage et de transfert d'une couche
FR2957189B1 (fr) * 2010-03-02 2012-04-27 Soitec Silicon On Insulator Procede de realisation d'une structure multicouche avec detourage post meulage.
JP2011205074A (ja) * 2010-03-03 2011-10-13 Toshiba Corp 半導体製造装置
EP4290563A3 (de) 2010-12-20 2024-03-20 EV Group E. Thallner GmbH Aufnahmeeinrichtung zur halterung von wafern
FR2969373B1 (fr) * 2010-12-20 2013-07-19 St Microelectronics Crolles 2 Procede d'assemblage de deux plaques et dispositif correspondant
JP5796412B2 (ja) * 2011-08-26 2015-10-21 三菱電機株式会社 半導体素子の製造方法
FR2980302A1 (fr) * 2011-09-20 2013-03-22 St Microelectronics Crolles 2 Procede de protection d'une couche d'un empilement vertical et dispositif correspondant
US9123754B2 (en) 2011-10-06 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding alignment tool and method
KR101544734B1 (ko) * 2011-11-22 2015-08-17 다즈모 가부시키가이샤 가압원판, 접합장치 및 접합방법
DE102012107899B4 (de) * 2012-04-25 2014-07-17 Taiwan Semiconductor Manufacturing Co., Ltd. Waferanordnung mit Trägerwafer und Herstellungsverfahren dafür
US9111982B2 (en) 2012-04-25 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer assembly with carrier wafer
WO2016147529A1 (ja) * 2015-03-16 2016-09-22 富士電機株式会社 半導体装置の製造方法
DE102015108901A1 (de) * 2015-06-05 2016-12-08 Ev Group E. Thallner Gmbh Verfahren zum Ausrichten von Substraten vor dem Bonden
US10867836B2 (en) * 2016-05-02 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer stack and fabrication method thereof
NL2018856B1 (en) * 2017-05-05 2018-11-14 Suss Microtec Lithography Gmbh Method and device for aligning a first substrate with a second substrate
JP6998149B2 (ja) * 2017-08-08 2022-01-18 株式会社ディスコ レーザー加工方法
US12237234B2 (en) * 2019-05-22 2025-02-25 VueReal Alignment process for the transfer setup
JP7436187B2 (ja) * 2019-11-25 2024-02-21 株式会社ディスコ ウエーハの加工方法
JP2024034443A (ja) * 2022-08-31 2024-03-13 キオクシア株式会社 位置決定方法および半導体装置の製造方法
CN116782738B (zh) * 2023-08-23 2023-10-20 青禾晶元(晋城)半导体材料有限公司 键合片的分离装置及其分离方法

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JPH03183130A (ja) * 1989-12-12 1991-08-09 Sony Corp 半導体基板の製造方法
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US5869386A (en) * 1995-09-28 1999-02-09 Nec Corporation Method of fabricating a composite silicon-on-insulator substrate
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JPH11274442A (ja) 1998-03-26 1999-10-08 Sony Corp 基板はり合わせ方法
JP3675642B2 (ja) 1998-06-26 2005-07-27 三菱住友シリコン株式会社 誘電体分離ウェーハの製造方法
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
US6362069B1 (en) * 2000-12-28 2002-03-26 The Trustees Of Princeton University Long-wavelength VCSELs and method of manufacturing same

Also Published As

Publication number Publication date
EP1278245A4 (de) 2005-06-15
US6830985B2 (en) 2004-12-14
TW483042B (en) 2002-04-11
DE60141462D1 (de) 2010-04-15
US20030092244A1 (en) 2003-05-15
JP3991300B2 (ja) 2007-10-17
JP2001313383A (ja) 2001-11-09
EP1278245B1 (de) 2010-03-03
WO2001084633A1 (en) 2001-11-08
EP1278245A1 (de) 2003-01-22

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