ATE457083T1 - Halbleitervorrichtung mit sicherungen und verfahren zu deren herstellung - Google Patents

Halbleitervorrichtung mit sicherungen und verfahren zu deren herstellung

Info

Publication number
ATE457083T1
ATE457083T1 AT01933867T AT01933867T ATE457083T1 AT E457083 T1 ATE457083 T1 AT E457083T1 AT 01933867 T AT01933867 T AT 01933867T AT 01933867 T AT01933867 T AT 01933867T AT E457083 T1 ATE457083 T1 AT E457083T1
Authority
AT
Austria
Prior art keywords
fuses
substrate
semiconductor device
production
conductor
Prior art date
Application number
AT01933867T
Other languages
English (en)
Inventor
Hermanus Effing
Alfred Hamstra
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Application granted granted Critical
Publication of ATE457083T1 publication Critical patent/ATE457083T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5382—Adaptable interconnections, e.g. for engineering changes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
AT01933867T 2000-05-11 2001-04-23 Halbleitervorrichtung mit sicherungen und verfahren zu deren herstellung ATE457083T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00201684 2000-05-11
PCT/EP2001/004567 WO2001086718A2 (en) 2000-05-11 2001-04-23 Semiconductor device with fuses and method of manufacturing same

Publications (1)

Publication Number Publication Date
ATE457083T1 true ATE457083T1 (de) 2010-02-15

Family

ID=8171480

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01933867T ATE457083T1 (de) 2000-05-11 2001-04-23 Halbleitervorrichtung mit sicherungen und verfahren zu deren herstellung

Country Status (7)

Country Link
US (1) US6590284B2 (de)
EP (1) EP1287557B1 (de)
JP (1) JP2003533048A (de)
CN (1) CN1207778C (de)
AT (1) ATE457083T1 (de)
DE (1) DE60141242D1 (de)
WO (1) WO2001086718A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7242199B2 (en) * 2005-04-21 2007-07-10 Hewlett-Packard Development Company, L.P. Active interconnects and control points in integrated circuits
US7693596B2 (en) * 2005-12-14 2010-04-06 Dell Products L.P. System and method for configuring information handling system integrated circuits
US8253526B2 (en) * 2007-05-07 2012-08-28 Texas Instruments Incorporated Termination compensation for differential signals on glass
KR20100104855A (ko) * 2009-03-19 2010-09-29 삼성전자주식회사 퓨즈를 포함하는 반도체 소자 패키지
US9378443B2 (en) 2009-05-14 2016-06-28 Ascensia Diabetes Care Holding Ag Calibration coded sensors and apparatus, systems and methods for reading same
US9632055B2 (en) * 2010-11-12 2017-04-25 Ascensia Diabetes Care Holdings Ag Auto-coded analyte sensors and apparatus, systems, and methods for detecting same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3881175A (en) * 1973-12-26 1975-04-29 Lsi Systems Inc Integrated circuit SOS memory subsystem and method of making same
US6222212B1 (en) * 1994-01-27 2001-04-24 Integrated Device Technology, Inc. Semiconductor device having programmable interconnect layers
JP2546192B2 (ja) * 1994-09-30 1996-10-23 日本電気株式会社 フィルムキャリア半導体装置
JPH08242046A (ja) * 1995-03-03 1996-09-17 Rohm Co Ltd 温度ヒューズ付き半導体装置の構造
US5914649A (en) * 1997-03-28 1999-06-22 Hitachi Chemical Company, Ltd. Chip fuse and process for production thereof
JPH11163217A (ja) * 1997-09-08 1999-06-18 Shinko Electric Ind Co Ltd 半導体装置
JPH11154717A (ja) * 1997-11-20 1999-06-08 Citizen Watch Co Ltd 半導体装置
JPH11346061A (ja) * 1998-06-02 1999-12-14 Hitachi Ltd コンデンサ内蔵回路基板およびその製造方法
JP2000049250A (ja) * 1998-07-30 2000-02-18 Toshiba Microelectronics Corp 半導体装置

Also Published As

Publication number Publication date
WO2001086718A2 (en) 2001-11-15
DE60141242D1 (de) 2010-03-25
CN1386303A (zh) 2002-12-18
EP1287557B1 (de) 2010-02-03
US20010052646A1 (en) 2001-12-20
JP2003533048A (ja) 2003-11-05
CN1207778C (zh) 2005-06-22
WO2001086718A3 (en) 2002-04-04
US6590284B2 (en) 2003-07-08
EP1287557A2 (de) 2003-03-05

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties