ATE429709T1 - Verfahren zur herstellung von elektronischen hybridschaltungen für aktive medizinische implantierbare vorrichtungen - Google Patents

Verfahren zur herstellung von elektronischen hybridschaltungen für aktive medizinische implantierbare vorrichtungen

Info

Publication number
ATE429709T1
ATE429709T1 AT02290136T AT02290136T ATE429709T1 AT E429709 T1 ATE429709 T1 AT E429709T1 AT 02290136 T AT02290136 T AT 02290136T AT 02290136 T AT02290136 T AT 02290136T AT E429709 T1 ATE429709 T1 AT E429709T1
Authority
AT
Austria
Prior art keywords
wafers
hybrid electronic
plate
electronic circuits
circuits
Prior art date
Application number
AT02290136T
Other languages
English (en)
Inventor
Campenhout Yves Van
Dominique Gilet
Thierry Legay
Original Assignee
Ela Medical Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ela Medical Sa filed Critical Ela Medical Sa
Application granted granted Critical
Publication of ATE429709T1 publication Critical patent/ATE429709T1/de

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrotherapy Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
AT02290136T 2001-01-19 2002-01-18 Verfahren zur herstellung von elektronischen hybridschaltungen für aktive medizinische implantierbare vorrichtungen ATE429709T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0100726A FR2819935B1 (fr) 2001-01-19 2001-01-19 Procede de fabrication de circuits electroniques hybrides pour dispositifs medicaux implantables actifs

Publications (1)

Publication Number Publication Date
ATE429709T1 true ATE429709T1 (de) 2009-05-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
AT02290136T ATE429709T1 (de) 2001-01-19 2002-01-18 Verfahren zur herstellung von elektronischen hybridschaltungen für aktive medizinische implantierbare vorrichtungen

Country Status (6)

Country Link
US (1) US6898845B2 (de)
EP (1) EP1225630B8 (de)
JP (1) JP4202024B2 (de)
AT (1) ATE429709T1 (de)
DE (1) DE60232039D1 (de)
FR (1) FR2819935B1 (de)

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JP5221150B2 (ja) 2005-02-01 2013-06-26 セカンド サイト メディカル プロダクツ インコーポレイテッド 超小型埋め込み型の被覆された装置

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Publication number Priority date Publication date Assignee Title
JPS5111772B1 (de) * 1969-11-03 1976-04-14
US4246595A (en) * 1977-03-08 1981-01-20 Matsushita Electric Industrial Co., Ltd. Electronics circuit device and method of making the same
DE3442131A1 (de) * 1984-11-17 1986-05-22 Messerschmitt-Bölkow-Blohm GmbH, 8012 Ottobrunn Verfahren zum einkapseln von mikroelektronischen halbleiter- und schichtschaltungen
US5159751A (en) * 1990-02-05 1992-11-03 Motorola, Inc. Method of manufacturing electronic module assembly
JPH04348045A (ja) * 1990-05-20 1992-12-03 Hitachi Ltd 半導体装置及びその製造方法
KR940008066A (ko) * 1992-09-18 1994-04-28 윌리엄 이. 힐러 집적 회로용 다중층 리드 프레임 어셈블리 및 방법
ES2122620T3 (es) * 1994-05-27 1998-12-16 Ake Gustafson Procedimiento de realizacion de un modulo electronico y modulo electronico obtenido segun este procedimiento.
US5782891A (en) * 1994-06-16 1998-07-21 Medtronic, Inc. Implantable ceramic enclosure for pacing, neurological, and other medical applications in the human body
US5434362A (en) * 1994-09-06 1995-07-18 Motorola, Inc. Flexible circuit board assembly and method
JP2570637B2 (ja) * 1994-11-28 1997-01-08 日本電気株式会社 Ｍｃｍキャリア
CH689217A5 (fr) * 1995-04-25 1998-12-15 Valtronic S A Procédé de montage de puces électroniques.
US5963429A (en) * 1997-08-20 1999-10-05 Sulzer Intermedics Inc. Printed circuit substrate with cavities for encapsulating integrated circuits
FR2772516B1 (fr) * 1997-12-12 2003-07-04 Ela Medical Sa Circuit electronique, notamment pour un dispositif medical implantable actif tel qu'un stimulateur ou defibrillateur cardiaque, et son procede de realisation
US5954751A (en) * 1998-01-15 1999-09-21 Intermedics Inc. Implantable defibrillator with stacked transistor subassemblies
US5987358A (en) 1998-02-17 1999-11-16 Intermedics, Inc. Semiconductor device packaging and method of fabrication

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EP1225630A1 (de) 2002-07-24
FR2819935A1 (fr) 2002-07-26
DE60232039D1 (de) 2009-06-04
JP4202024B2 (ja) 2008-12-24
US20020147478A1 (en) 2002-10-10
US6898845B2 (en) 2005-05-31
EP1225630B1 (de) 2009-04-22
EP1225630B8 (de) 2009-08-12
JP2002320681A (ja) 2002-11-05
FR2819935B1 (fr) 2003-04-25

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