ATE419650T1 - Herstellungsverfahren eines halbleiterfestwertspeichers - Google Patents

Herstellungsverfahren eines halbleiterfestwertspeichers

Info

Publication number
ATE419650T1
ATE419650T1 AT03718996T AT03718996T ATE419650T1 AT E419650 T1 ATE419650 T1 AT E419650T1 AT 03718996 T AT03718996 T AT 03718996T AT 03718996 T AT03718996 T AT 03718996T AT E419650 T1 ATE419650 T1 AT E419650T1
Authority
AT
Austria
Prior art keywords
conductors
memory
active regions
planarized
conductive layer
Prior art date
Application number
AT03718996T
Other languages
English (en)
Inventor
Schaijk Robertus Van
Michiel Slotboom
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE419650T1 publication Critical patent/ATE419650T1/de

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324Gate electrodes for transistors with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40114Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AT03718996T 2002-05-07 2003-05-05 Herstellungsverfahren eines halbleiterfestwertspeichers ATE419650T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02076830 2002-05-07

Publications (1)

Publication Number Publication Date
ATE419650T1 true ATE419650T1 (de) 2009-01-15

Family

ID=29414763

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03718996T ATE419650T1 (de) 2002-05-07 2003-05-05 Herstellungsverfahren eines halbleiterfestwertspeichers

Country Status (10)

Country Link
US (1) US6991982B2 (de)
EP (1) EP1506574B1 (de)
JP (1) JP2005524992A (de)
KR (1) KR20040111581A (de)
CN (1) CN1315181C (de)
AT (1) ATE419650T1 (de)
AU (1) AU2003223028A1 (de)
DE (1) DE60325581D1 (de)
TW (1) TWI289343B (de)
WO (1) WO2003096413A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100683389B1 (ko) * 2005-09-20 2007-02-15 동부일렉트로닉스 주식회사 플래시 메모리의 셀 트랜지스터 및 그 제조 방법
CN100578669C (zh) * 2008-01-28 2010-01-06 南京航空航天大学 一种非易失存储器
US10797063B2 (en) * 2018-01-10 2020-10-06 Ememory Technology Inc. Single-poly nonvolatile memory unit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5712180A (en) * 1992-01-14 1998-01-27 Sundisk Corporation EEPROM with split gate source side injection
US6063702A (en) * 1997-01-27 2000-05-16 Chartered Semiconductor Manufacturing, Ltd. Global planarization method for inter level dielectric layers using IDL blocks
EP1080490B1 (de) * 1999-03-10 2007-12-26 Nxp B.V. Verfahren zur herstellung eines halbleiterbauelements mit einem bipolartransistor und einem kondensator
TW484228B (en) * 1999-08-31 2002-04-21 Toshiba Corp Non-volatile semiconductor memory device and the manufacturing method thereof
KR100841891B1 (ko) * 2000-03-08 2008-06-30 엔엑스피 비 브이 반도체 디바이스 및 그 제조 방법
GB0018028D0 (en) * 2000-07-24 2000-09-13 Koninkl Philips Electronics Nv Semiconductor devices and their manufacture
US6512263B1 (en) * 2000-09-22 2003-01-28 Sandisk Corporation Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming

Also Published As

Publication number Publication date
CN1653609A (zh) 2005-08-10
EP1506574B1 (de) 2008-12-31
DE60325581D1 (de) 2009-02-12
JP2005524992A (ja) 2005-08-18
US20050207209A1 (en) 2005-09-22
TW200401410A (en) 2004-01-16
WO2003096413A1 (en) 2003-11-20
EP1506574A1 (de) 2005-02-16
KR20040111581A (ko) 2004-12-31
CN1315181C (zh) 2007-05-09
TWI289343B (en) 2007-11-01
AU2003223028A1 (en) 2003-11-11
US6991982B2 (en) 2006-01-31

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Legal Events

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