ATE393982T1 - Hybride kompensierte ausgangspufferstruktur - Google Patents

Hybride kompensierte ausgangspufferstruktur

Info

Publication number
ATE393982T1
ATE393982T1 AT04754884T AT04754884T ATE393982T1 AT E393982 T1 ATE393982 T1 AT E393982T1 AT 04754884 T AT04754884 T AT 04754884T AT 04754884 T AT04754884 T AT 04754884T AT E393982 T1 ATE393982 T1 AT E393982T1
Authority
AT
Austria
Prior art keywords
output buffer
buffer structure
compensated output
hybrid
circuit
Prior art date
Application number
AT04754884T
Other languages
English (en)
Inventor
James Chandler
John Zumkehr
Arnaud Forestier
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE393982T1 publication Critical patent/ATE393982T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)
  • Transmitters (AREA)
AT04754884T 2003-06-27 2004-06-09 Hybride kompensierte ausgangspufferstruktur ATE393982T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/608,633 US6922077B2 (en) 2003-06-27 2003-06-27 Hybrid compensated buffer design

Publications (1)

Publication Number Publication Date
ATE393982T1 true ATE393982T1 (de) 2008-05-15

Family

ID=33540629

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04754884T ATE393982T1 (de) 2003-06-27 2004-06-09 Hybride kompensierte ausgangspufferstruktur

Country Status (9)

Country Link
US (2) US6922077B2 (de)
EP (1) EP1639708B1 (de)
JP (1) JP2007520904A (de)
KR (1) KR20060025198A (de)
CN (1) CN100385793C (de)
AT (1) ATE393982T1 (de)
DE (1) DE602004013443T2 (de)
TW (2) TWI284458B (de)
WO (1) WO2005006554A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7095245B2 (en) * 2003-11-14 2006-08-22 Intel Corporation Internal voltage reference for memory interface
US7671630B2 (en) * 2005-07-29 2010-03-02 Synopsys, Inc. USB 2.0 HS voltage-mode transmitter with tuned termination resistance
US7522659B2 (en) * 2005-09-19 2009-04-21 Synopsys, Inc. Universal serial bus (USB) 2.0 legacy full speed and low speed (FS/LS) mode driver
KR100733415B1 (ko) * 2005-09-29 2007-06-29 주식회사 하이닉스반도체 반도체 메모리 소자 및 그의 비트라인 센스앰프 구동방법
CN1980057B (zh) * 2005-12-01 2011-10-26 瑞昱半导体股份有限公司 输出驱动电路的阻抗匹配装置
KR100820783B1 (ko) 2007-03-02 2008-04-11 주식회사 하이닉스반도체 미스매치를 줄인 온 다이 터미네이션 장치
US7729168B2 (en) 2007-06-28 2010-06-01 Intel Corporation Reduced signal level support for memory devices
US8022730B2 (en) * 2009-10-13 2011-09-20 Himax Technologies Limited Driving circuit with slew-rate enhancement circuit
DE102009057107B4 (de) * 2009-12-04 2011-11-10 Micronas Gmbh Verfahren und Schaltungsanordnung zum Steuern von Schalttransistoren einer integrierten Schaltung
US8125245B2 (en) * 2010-06-21 2012-02-28 Synopsys, Inc. Circuitry for matching the up and down impedances of a voltage-mode transmitter
US9571155B2 (en) * 2014-08-25 2017-02-14 Samsung Display Co., Ltd. Method of startup sequence for a panel interface
GB2567393B (en) * 2016-08-26 2022-04-06 Univ Central South Preparation method of phosphotungstic acid
US10355690B2 (en) * 2016-09-28 2019-07-16 Intel Corporation High speed driver with adaptive termination impedance
US10942220B2 (en) 2019-04-25 2021-03-09 Teradyne, Inc. Voltage driver with supply current stabilization
US11119155B2 (en) 2019-04-25 2021-09-14 Teradyne, Inc. Voltage driver circuit
US10761130B1 (en) * 2019-04-25 2020-09-01 Teradyne, Inc. Voltage driver circuit calibration
US11283436B2 (en) 2019-04-25 2022-03-22 Teradyne, Inc. Parallel path delay line

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US555441A (en) * 1896-02-25 Folding bed
US4449441A (en) * 1982-03-09 1984-05-22 Westinghouse Electric Corp. Electromagnetic projectile launcher with magnetic spin stabilization
US5559441A (en) 1995-04-19 1996-09-24 Hewlett-Packard Company Transmission line driver with self adjusting output impedance
US6114895A (en) 1997-10-29 2000-09-05 Agilent Technologies Integrated circuit assembly having output pads with application specific characteristics and method of operation
US6133749A (en) * 1999-01-04 2000-10-17 International Business Machines Corporation Variable impedance output driver circuit using analog biases to match driver output impedance to load input impedance
US6194924B1 (en) 1999-04-22 2001-02-27 Agilent Technologies Inc. Multi-function controlled impedance output driver
JP2001217705A (ja) * 2000-01-31 2001-08-10 Fujitsu Ltd Ｌｓｉデバイス
US6445316B1 (en) * 2000-09-29 2002-09-03 Intel Corporation Universal impedance control for wide range loaded signals
US6445245B1 (en) 2000-10-06 2002-09-03 Xilinx, Inc. Digitally controlled impedance for I/O of an integrated circuit device

Also Published As

Publication number Publication date
US7071728B2 (en) 2006-07-04
WO2005006554A1 (en) 2005-01-20
CN100385793C (zh) 2008-04-30
TW200501577A (en) 2005-01-01
TWI279982B (en) 2007-04-21
DE602004013443T2 (de) 2009-06-04
US20050110517A1 (en) 2005-05-26
TW200516851A (en) 2005-05-16
CN1813405A (zh) 2006-08-02
KR20060025198A (ko) 2006-03-20
US6922077B2 (en) 2005-07-26
EP1639708A1 (de) 2006-03-29
EP1639708B1 (de) 2008-04-30
US20040263204A1 (en) 2004-12-30
JP2007520904A (ja) 2007-07-26
DE602004013443D1 (de) 2008-06-12
TWI284458B (en) 2007-07-21

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Legal Events

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