ATE373844T1 - Rechneradapterkarte für die kombinierung von eingang-/ausgangfertigstellungsberichten und verwendung derselben - Google Patents

Rechneradapterkarte für die kombinierung von eingang-/ausgangfertigstellungsberichten und verwendung derselben

Info

Publication number
ATE373844T1
ATE373844T1 AT00923098T AT00923098T ATE373844T1 AT E373844 T1 ATE373844 T1 AT E373844T1 AT 00923098 T AT00923098 T AT 00923098T AT 00923098 T AT00923098 T AT 00923098T AT E373844 T1 ATE373844 T1 AT E373844T1
Authority
AT
Austria
Prior art keywords
input
requests
combining
adapter card
output completion
Prior art date
Application number
AT00923098T
Other languages
English (en)
Inventor
Charles Micalizzi
Thanh Nghiem
Richard Romaniec
Toan Nguyen
Original Assignee
Qlogic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qlogic Corp filed Critical Qlogic Corp
Application granted granted Critical
Publication of ATE373844T1 publication Critical patent/ATE373844T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Input From Keyboards Or The Like (AREA)
  • Multi Processors (AREA)
  • Debugging And Monitoring (AREA)
AT00923098T 1999-03-31 2000-03-29 Rechneradapterkarte für die kombinierung von eingang-/ausgangfertigstellungsberichten und verwendung derselben ATE373844T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/282,341 US6434630B1 (en) 1999-03-31 1999-03-31 Host adapter for combining I/O completion reports and method of using the same

Publications (1)

Publication Number Publication Date
ATE373844T1 true ATE373844T1 (de) 2007-10-15

Family

ID=23081068

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00923098T ATE373844T1 (de) 1999-03-31 2000-03-29 Rechneradapterkarte für die kombinierung von eingang-/ausgangfertigstellungsberichten und verwendung derselben

Country Status (9)

Country Link
US (1) US6434630B1 (de)
EP (1) EP1163595B1 (de)
JP (1) JP2002540526A (de)
KR (1) KR100677538B1 (de)
AT (1) ATE373844T1 (de)
AU (1) AU4327800A (de)
CA (1) CA2367890C (de)
DE (1) DE60036465T2 (de)
WO (1) WO2000058843A1 (de)

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US7219263B1 (en) 2003-10-29 2007-05-15 Qlogic, Corporation Method and system for minimizing memory corruption
US7930377B2 (en) 2004-04-23 2011-04-19 Qlogic, Corporation Method and system for using boot servers in networks
US7669190B2 (en) 2004-05-18 2010-02-23 Qlogic, Corporation Method and system for efficiently recording processor events in host bus adapters
US7577772B2 (en) * 2004-09-08 2009-08-18 Qlogic, Corporation Method and system for optimizing DMA channel selection
US20060064531A1 (en) * 2004-09-23 2006-03-23 Alston Jerald K Method and system for optimizing data transfer in networks
US7676611B2 (en) 2004-10-01 2010-03-09 Qlogic, Corporation Method and system for processing out of orders frames
US7398335B2 (en) * 2004-11-22 2008-07-08 Qlogic, Corporation Method and system for DMA optimization in host bus adapters
US7164425B2 (en) * 2004-12-21 2007-01-16 Qlogic Corporation Method and system for high speed network application
US7392437B2 (en) 2005-01-20 2008-06-24 Qlogic, Corporation Method and system for testing host bus adapters
US7853960B1 (en) * 2005-02-25 2010-12-14 Vmware, Inc. Efficient virtualization of input/output completions for a virtual device
US7231480B2 (en) * 2005-04-06 2007-06-12 Qlogic, Corporation Method and system for receiver detection in PCI-Express devices
US7281077B2 (en) * 2005-04-06 2007-10-09 Qlogic, Corporation Elastic buffer module for PCI express devices
JP2007012021A (ja) * 2005-06-01 2007-01-18 Sony Corp 情報処理装置および情報処理方法、並びにプログラム
US7461195B1 (en) 2006-03-17 2008-12-02 Qlogic, Corporation Method and system for dynamically adjusting data transfer rates in PCI-express devices
US7743195B2 (en) * 2006-12-27 2010-06-22 Intel Corporation Interrupt mailbox in host memory
US7716397B2 (en) * 2007-07-03 2010-05-11 Lsi Corporation Methods and systems for interprocessor message exchange between devices using only write bus transactions
JP5101195B2 (ja) * 2007-07-09 2012-12-19 株式会社東芝 インタフェースコントローラ
US8458730B2 (en) * 2008-02-05 2013-06-04 International Business Machines Corporation Multi-level driver configuration
US9032128B2 (en) * 2008-04-28 2015-05-12 Hewlett-Packard Development Company, L.P. Method and system for generating and delivering inter-processor interrupts in a multi-core processor and in certain shared memory multi-processor systems
US20100005199A1 (en) * 2008-07-07 2010-01-07 Texas Instruments Incorporated Direct memory access (dma) data transfers with reduced overhead
JP5395797B2 (ja) * 2008-08-20 2014-01-22 パナソニック株式会社 通信装置、及び通信制御方法
US7853726B2 (en) * 2008-10-06 2010-12-14 International Business Machines Corporation FCP command-data matching for write operations
FR2952937B1 (fr) 2009-11-20 2013-02-08 Chaire Europeenne De Chimie Now Pour Un Developpement Durable Nouvelles resines de type phenoplastes obtenues a partir de composes phenoliques et de durcisseurs macromoleculaire portant des fonctions aldehydes
US8719843B2 (en) * 2011-07-27 2014-05-06 Intel Corporation Virtualizable and forward-compatible hardware-software interface
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US9298652B2 (en) * 2013-03-15 2016-03-29 Microsoft Technology Licensing, Llc Moderated completion signaling
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Also Published As

Publication number Publication date
KR100677538B1 (ko) 2007-02-01
KR20010104732A (ko) 2001-11-26
CA2367890A1 (en) 2000-10-05
DE60036465D1 (de) 2007-10-31
AU4327800A (en) 2000-10-16
WO2000058843A1 (en) 2000-10-05
EP1163595B1 (de) 2007-09-19
JP2002540526A (ja) 2002-11-26
US6434630B1 (en) 2002-08-13
EP1163595A1 (de) 2001-12-19
CA2367890C (en) 2007-05-29
DE60036465T2 (de) 2008-06-12

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