ATE368939T1 - Bildung einer silicium-germanium-auf-isolator- struktur durch oxidation einer vergrabenen porösen siliciumschicht - Google Patents

Bildung einer silicium-germanium-auf-isolator- struktur durch oxidation einer vergrabenen porösen siliciumschicht

Info

Publication number
ATE368939T1
ATE368939T1 AT04809708T AT04809708T ATE368939T1 AT E368939 T1 ATE368939 T1 AT E368939T1 AT 04809708 T AT04809708 T AT 04809708T AT 04809708 T AT04809708 T AT 04809708T AT E368939 T1 ATE368939 T1 AT E368939T1
Authority
AT
Austria
Prior art keywords
oxidation
germanium
formation
silicon layer
insulator structure
Prior art date
Application number
AT04809708T
Other languages
German (de)
English (en)
Inventor
Stephen Bedell
Kwang Su Choe
Keith Fogel
Devendra Sadana
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE368939T1 publication Critical patent/ATE368939T1/de

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22F—CHANGING THE PHYSICAL STRUCTURE OF NON-FERROUS METALS AND NON-FERROUS ALLOYS
    • C22F1/00—Changing the physical structure of non-ferrous metals or alloys by heat treatment or by hot or cold working
    • C22F1/10—Changing the physical structure of non-ferrous metals or alloys by heat treatment or by hot or cold working of nickel or cobalt or alloys based thereon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76245—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using full isolation by porous oxide silicon, i.e. FIPOS techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thermal Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Silicates, Zeolites, And Molecular Sieves (AREA)
AT04809708T 2003-09-12 2004-09-10 Bildung einer silicium-germanium-auf-isolator- struktur durch oxidation einer vergrabenen porösen siliciumschicht ATE368939T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/662,028 US7125458B2 (en) 2003-09-12 2003-09-12 Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer

Publications (1)

Publication Number Publication Date
ATE368939T1 true ATE368939T1 (de) 2007-08-15

Family

ID=34274005

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04809708T ATE368939T1 (de) 2003-09-12 2004-09-10 Bildung einer silicium-germanium-auf-isolator- struktur durch oxidation einer vergrabenen porösen siliciumschicht

Country Status (9)

Country Link
US (1) US7125458B2 (enExample)
EP (1) EP1665340B1 (enExample)
JP (1) JP4856544B2 (enExample)
KR (1) KR100856988B1 (enExample)
CN (1) CN100429761C (enExample)
AT (1) ATE368939T1 (enExample)
DE (1) DE602004007940T2 (enExample)
TW (1) TWI330388B (enExample)
WO (1) WO2005031810A2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7566482B2 (en) * 2003-09-30 2009-07-28 International Business Machines Corporation SOI by oxidation of porous silicon
US7172930B2 (en) * 2004-07-02 2007-02-06 International Business Machines Corporation Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer
US7767541B2 (en) * 2005-10-26 2010-08-03 International Business Machines Corporation Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods
US7833884B2 (en) * 2007-11-02 2010-11-16 International Business Machines Corporation Strained semiconductor-on-insulator by Si:C combined with porous process
US7772096B2 (en) * 2008-07-10 2010-08-10 International Machines Corporation Formation of SOI by oxidation of silicon with engineered porosity gradient
FR2935194B1 (fr) * 2008-08-22 2010-10-08 Commissariat Energie Atomique Procede de realisation de structures geoi localisees, obtenues par enrichissement en germanium
US8618554B2 (en) * 2010-11-08 2013-12-31 International Business Machines Corporation Method to reduce ground-plane poisoning of extremely-thin SOI (ETSOI) layer with thin buried oxide
EP2761636A4 (en) 2011-09-30 2015-12-02 Intel Corp METHOD FOR INCREASING THE ENERGY DENSITY AND THE EFFICIENT OUTPUT POWER OF AN ENERGY STORAGE DEVICE
US8518807B1 (en) * 2012-06-22 2013-08-27 International Business Machines Corporation Radiation hardened SOI structure and method of making same
US9087716B2 (en) * 2013-07-15 2015-07-21 Globalfoundries Inc. Channel semiconductor alloy layer growth adjusted by impurity ion implantation
US9343303B2 (en) 2014-03-20 2016-05-17 Samsung Electronics Co., Ltd. Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices
US10032870B2 (en) 2015-03-12 2018-07-24 Globalfoundries Inc. Low defect III-V semiconductor template on porous silicon
US9899274B2 (en) 2015-03-16 2018-02-20 International Business Machines Corporation Low-cost SOI FinFET technology
US10833175B2 (en) * 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon
US20190131454A1 (en) * 2017-11-01 2019-05-02 Qualcomm Incorporated Semiconductor device with strained silicon layers on porous silicon
CN112908849A (zh) * 2021-01-28 2021-06-04 上海华力集成电路制造有限公司 一种形成SiGe沟道的热处理方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104090A (en) 1977-02-24 1978-08-01 International Business Machines Corporation Total dielectric isolation utilizing a combination of reactive ion etching, anodic etching, and thermal oxidation
JPS5831730B2 (ja) * 1979-10-15 1983-07-08 松下電器産業株式会社 半導体装置の製造方法
JPS592185B2 (ja) * 1980-02-04 1984-01-17 日本電信電話株式会社 半導体基体内への絶縁領域の形成法
KR960002765B1 (ko) 1992-12-22 1996-02-26 금성일렉트론주식회사 절연체 위에 단결정 반도체 제조방법
US6376859B1 (en) * 1998-07-29 2002-04-23 Texas Instruments Incorporated Variable porosity porous silicon isolation
US5950094A (en) * 1999-02-18 1999-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating fully dielectric isolated silicon (FDIS)
JP4212228B2 (ja) * 1999-09-09 2009-01-21 株式会社東芝 半導体装置の製造方法
JP2002305293A (ja) * 2001-04-06 2002-10-18 Canon Inc 半導体部材の製造方法及び半導体装置の製造方法
US6812116B2 (en) * 2002-12-13 2004-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance

Also Published As

Publication number Publication date
EP1665340B1 (en) 2007-08-01
DE602004007940T2 (de) 2008-04-24
EP1665340A2 (en) 2006-06-07
WO2005031810A2 (en) 2005-04-07
CN1957458A (zh) 2007-05-02
US20050056352A1 (en) 2005-03-17
JP2007505502A (ja) 2007-03-08
JP4856544B2 (ja) 2012-01-18
KR20060061839A (ko) 2006-06-08
KR100856988B1 (ko) 2008-09-04
TWI330388B (en) 2010-09-11
TW200516666A (en) 2005-05-16
CN100429761C (zh) 2008-10-29
US7125458B2 (en) 2006-10-24
WO2005031810A3 (en) 2005-06-23
DE602004007940D1 (de) 2007-09-13

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