ATE363732T1 - Verbesserungen in bezug auf integrierte schaltungen - Google Patents

Verbesserungen in bezug auf integrierte schaltungen

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Publication number
ATE363732T1
ATE363732T1 AT97310336T AT97310336T ATE363732T1 AT E363732 T1 ATE363732 T1 AT E363732T1 AT 97310336 T AT97310336 T AT 97310336T AT 97310336 T AT97310336 T AT 97310336T AT E363732 T1 ATE363732 T1 AT E363732T1
Authority
AT
Austria
Prior art keywords
integrated circuits
bondable
copper lead
barrier
layer
Prior art date
Application number
AT97310336T
Other languages
English (en)
Inventor
Taylor R Efland
Quang X Mai
Charles E Williams
Stephen A Keller
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of ATE363732T1 publication Critical patent/ATE363732T1/de

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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233Copper alloys
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    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
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    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)
AT97310336T 1996-12-19 1997-12-19 Verbesserungen in bezug auf integrierte schaltungen ATE363732T1 (de)

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Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268291B1 (en) 1995-12-29 2001-07-31 International Business Machines Corporation Method for forming electromigration-resistant structures by doping
US6261941B1 (en) * 1998-02-12 2001-07-17 Georgia Tech Research Corp. Method for manufacturing a multilayer wiring substrate
JP3378505B2 (ja) * 1998-06-23 2003-02-17 株式会社東芝 半導体装置およびその製造方法
US7381642B2 (en) * 2004-09-23 2008-06-03 Megica Corporation Top layers of metal for integrated circuits
US6495442B1 (en) * 2000-10-18 2002-12-17 Magic Corporation Post passivation interconnection schemes on top of the IC chips
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US7405149B1 (en) * 1998-12-21 2008-07-29 Megica Corporation Post passivation method for semiconductor chip or wafer
US6180505B1 (en) * 1999-01-07 2001-01-30 International Business Machines Corporation Process for forming a copper-containing film
US6133136A (en) * 1999-05-19 2000-10-17 International Business Machines Corporation Robust interconnect structure
US6790757B1 (en) * 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
US7271489B2 (en) 2003-10-15 2007-09-18 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US7372161B2 (en) * 2000-10-18 2008-05-13 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US6776893B1 (en) 2000-11-20 2004-08-17 Enthone Inc. Electroplating chemistry for the CU filling of submicron features of VLSI/ULSI interconnect
US6462426B1 (en) * 2000-12-14 2002-10-08 National Semiconductor Corporation Barrier pad for wafer level chip scale packages
JP2002329722A (ja) * 2001-04-27 2002-11-15 Nec Corp 半導体装置及びその製造方法
TW561805B (en) * 2001-05-16 2003-11-11 Unimicron Technology Corp Fabrication method of micro-via
US8368150B2 (en) * 2003-03-17 2013-02-05 Megica Corporation High performance IC chip having discrete decoupling capacitors attached to its IC surface
US7319277B2 (en) * 2003-05-08 2008-01-15 Megica Corporation Chip structure with redistribution traces
TWI229436B (en) * 2003-07-10 2005-03-11 Advanced Semiconductor Eng Wafer structure and bumping process
US7459790B2 (en) * 2003-10-15 2008-12-02 Megica Corporation Post passivation interconnection schemes on top of the IC chips
DE102004003538B3 (de) * 2004-01-23 2005-09-08 Infineon Technologies Ag Integrierte Halbleiterschaltung mit einer Logik- und Leistungs-Metallisierung ohne Intermetall-Dielektrikum und Verfahren zu ihrer Herstellung
JP2005268430A (ja) * 2004-03-17 2005-09-29 Nissan Motor Co Ltd オーミック電極構造体およびその製造方法
DE102004026232B4 (de) * 2004-05-28 2006-05-04 Infineon Technologies Ag Verfahren zum Ausbilden einer integrierten Halbleiterschaltungsanordnung
TWI240977B (en) * 2004-07-23 2005-10-01 Advanced Semiconductor Eng Structure and formation method for conductive bump
US7521805B2 (en) * 2004-10-12 2009-04-21 Megica Corp. Post passivation interconnection schemes on top of the IC chips
US7339275B2 (en) * 2004-11-22 2008-03-04 Freescale Semiconductor, Inc. Multi-chips semiconductor device assemblies and methods for fabricating the same
WO2006081321A2 (en) * 2005-01-25 2006-08-03 Hutchinson Technology Incorporated Single pass, dual thickness electroplating system for head suspension components
US20070087544A1 (en) * 2005-10-19 2007-04-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming improved bump structure
US8076779B2 (en) * 2005-11-08 2011-12-13 Lsi Corporation Reduction of macro level stresses in copper/low-K wafers
WO2007108439A1 (ja) * 2006-03-22 2007-09-27 Mitsubishi Electric Corporation 電力用半導体装置
DE102006044691B4 (de) 2006-09-22 2012-06-21 Infineon Technologies Ag Verfahren zum Herstellen einer Anschlussleitstruktur eines Bauelements
US7964934B1 (en) 2007-05-22 2011-06-21 National Semiconductor Corporation Fuse target and method of forming the fuse target in a copper process flow
US8030733B1 (en) 2007-05-22 2011-10-04 National Semiconductor Corporation Copper-compatible fuse target
US20090079080A1 (en) * 2007-09-24 2009-03-26 Infineon Technologies Ag Semiconductor Device with Multi-Layer Metallization
US7709956B2 (en) * 2008-09-15 2010-05-04 National Semiconductor Corporation Copper-topped interconnect structure that has thin and thick copper traces and method of forming the copper-topped interconnect structure
US20100181675A1 (en) * 2009-01-16 2010-07-22 Infineon Technologies Ag Semiconductor package with wedge bonded chip
US8759209B2 (en) * 2010-03-25 2014-06-24 Stats Chippac, Ltd. Semiconductor device and method of forming a dual UBM structure for lead free bump connections
JP2011222738A (ja) * 2010-04-09 2011-11-04 Renesas Electronics Corp 半導体装置の製造方法
TWI620290B (zh) * 2014-05-27 2018-04-01 聯華電子股份有限公司 導電墊結構及其製作方法
US9478512B2 (en) * 2015-02-11 2016-10-25 Dawning Leading Technology Inc. Semiconductor packaging structure having stacked seed layers
US9666546B1 (en) 2016-04-28 2017-05-30 Infineon Technologies Ag Multi-layer metal pads
US11127693B2 (en) 2017-08-25 2021-09-21 Infineon Technologies Ag Barrier for power metallization in semiconductor devices
US10304782B2 (en) 2017-08-25 2019-05-28 Infineon Technologies Ag Compressive interlayer having a defined crack-stop edge extension
US10734320B2 (en) * 2018-07-30 2020-08-04 Infineon Technologies Austria Ag Power metallization structure for semiconductor devices
US11031321B2 (en) 2019-03-15 2021-06-08 Infineon Technologies Ag Semiconductor device having a die pad with a dam-like configuration

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4000842A (en) * 1975-06-02 1977-01-04 National Semiconductor Corporation Copper-to-gold thermal compression gang bonding of interconnect leads to semiconductive devices
US4953003A (en) * 1987-05-21 1990-08-28 Siemens Aktiengesellschaft Power semiconductor device
US5226232A (en) * 1990-05-18 1993-07-13 Hewlett-Packard Company Method for forming a conductive pattern on an integrated circuit
US5130275A (en) * 1990-07-02 1992-07-14 Digital Equipment Corp. Post fabrication processing of semiconductor chips
US5209817A (en) * 1991-08-22 1993-05-11 International Business Machines Corporation Selective plating method for forming integral via and wiring layers
US5665991A (en) * 1992-03-13 1997-09-09 Texas Instruments Incorporated Device having current ballasting and busing over active area using a multi-level conductor process
US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
US5508229A (en) * 1994-05-24 1996-04-16 National Semiconductor Corporation Method for forming solder bumps in semiconductor devices
US5656858A (en) * 1994-10-19 1997-08-12 Nippondenso Co., Ltd. Semiconductor device with bump structure
US5468984A (en) * 1994-11-02 1995-11-21 Texas Instruments Incorporated ESD protection structure using LDMOS diodes with thick copper interconnect
US5545927A (en) * 1995-05-12 1996-08-13 International Business Machines Corporation Capped copper electrical interconnects
JP3304754B2 (ja) * 1996-04-11 2002-07-22 三菱電機株式会社 集積回路の多段埋め込み配線構造

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US6020640A (en) 2000-02-01
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DE69737762T2 (de) 2008-01-31
EP0849797B1 (de) 2007-05-30
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